Voltage controller and memory device including same

Patent metadata

Field	Value
Publication number	US-11189332-B2
Application number	US-202016842891-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	Oct 11, 2019
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A memory device includes a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller. The voltage controller includes a voltage driver that generates a control signal and an overdrive controller that generates an overdrive control signal that regulates the generating of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information. The voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.

First claim

What is claimed is:

1. A memory device, comprising:
a memory cell array including a plurality of memory cells storing data, a sense amplifier connected to the memory cell array, and a voltage controller,
wherein the voltage controller includes:
a voltage driver that generates a control signal; and
an overdrive controller that generates an overdrive control signal that regulates generation of the control signal in response to at least one of a result of a comparison between the control signal and a reference voltage, and process, voltage, temperature (PVT) information,
wherein the voltage driver adjusts the control signal in response to the overdrive control signal to generate an overdriven control signal and outputs the overdriven control signal to the sense amplifier.

2. The memory device of claim 1 , wherein the control signal is an array voltage, and the voltage driver adjusts a level of the array voltage to generate an overdriven array voltage.

3. The memory device of claim 1 , wherein the control signal is an array voltage, and wherein the voltage driver adjusts timing of the array voltage as output to the sense amplifier in order to generate the overdriven array voltage.

4. The memory device of claim 1 , wherein the PVT information is obtained during an electrical die sort (EDS) test process that tests electrical characteristics of the memory device before packaging of the memory device.

5. The memory device of claim 1 , further including an input and output circuit, wherein the PVT information includes a ZQ code that matches an ON-resistance of the input and output circuit to a predetermined ZQ resistance.

6. The memory device of claim 1 , further including an input and output circuit, wherein the PVT information includes a phase difference between a data signal (DQ) and a data strobe signal (DQS), as applied to the input and output circuit.

7. The memory device of claim 1 , wherein the control signal is an array voltage, and wherein the voltage controller further includes a PVT information mapping unit that stores mapping information between the PVT information and at least one control value for the array voltage.

8. A memory device, comprising:
a plurality of memory cells disposed at intersections of a plurality of word lines and a plurality of bitlines;
a sense amplifier connected to the plurality of bitlines and sense amplifying data stored in the plurality of memory cells;
an input and output circuit exchanging the data through a plurality of data lines using a data signal (DQ) and a data strobe signal (DQS); and
a voltage controller providing a control voltage to at least one of the plurality of memory cells and the sense amplifier,
wherein the voltage controller includes:
a voltage driver that generates the control voltage;
a first overdrive controller that generates a first overdrive control signal applied to the voltage controller to regulate generation of the control voltage in response to a change in an externally provided power supply voltage; and
a second overdrive controller that generates a second overdrive control signal applied to the voltage driver to regulate generation of the control voltage in response to at least one of a ZQ code that matches an ON-resistance of the input and output circuit to reference ZQ resistance, and a phase difference between the data signal (DQ) and the data strobe signal (DQS).

9. The memory device of claim 8 , further comprising a ZQ code generator that generates the ZQ code.

10. The memory device of claim 8 , further comprising a DQS timer that determines the phase difference between the data signal (DQ) and the data strobe signal (DQS).

11. The memory device of claim 8 , wherein the voltage controller further includes an selector configured to selectively output one of the first overdrive control signal and the second overdrive control signal.

12. The memory device of claim 11 , wherein the selector is further configured to select and output one of the first overdrive control signal and the second overdrive control signal in response to result of comparing a phase difference between the data signal (DQ) and the data strobe signal (DQS) with a first threshold.

13. The memory device of claim 12 , wherein the selector is configured to select and output the first overdrive control signal when the phase difference between the data signal (DQ) and the data strobe signal (DQS) is less than the first threshold.

14. The memory device of claim 12 , wherein the selector is configured to select and output the second overdrive control signal when the phase difference between the data signal (DQ) and the data strobe signal (DQS) is greater than or equal to the first threshold.

15. The memory device of claim 11 , wherein the voltage driver is configured to adjust a level of the control voltage in response to the first overdrive control signal.

16. The memory device of claim 11 , wherein the voltage driver is configured to adjust at least one of a level and timing of the control voltage in response to the second overdrive control signal.

17. A voltage controller, comprising:
a voltage driver configured to generate a control signal used to perform a bitline sensing operation of a memory device;
a first overdrive controller configured to generate a first overdrive control signal that regulates generation of the control signal by the voltage driver in response to a result of comparing the control signal with a reference voltage; and
a second overdrive controller configured to generate a second overdrive control signal that regulate generation of the control signal by the voltage driver in response to process, voltage, temperature (PVT) information,
wherein the PVT information includes at least one of a ZQ code that matches an ON-resistance of an input and output circuit of the memory device to a reference ZQ resistance, and a phase difference between a data signal (DQ) and a data strobe signal (DQS) as applied to the input and output circuit.

18. The voltage controller of claim 17 , wherein the control signal is an array voltage and the voltage driver is configured to adjust a level of the array voltage in response to the first overdrive control signal.

19. The voltage controller of claim 17 , wherein the control signal is an array voltage and the voltage driver is configured to adjust at least one of a level of the array voltage and output timing in response to the second overdrive control signal.

20. The voltage controller of claim 17 , wherein the control signal is an array voltage, and
the voltage controlled further comprising a PVT information mapping unit that stores mapping information between the PVT information and at least one control value of the array voltage.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jeong Jaewoo
• Moon Byongmo

Classifications

• G11C2207/2254

  Calibration · CPC title

• G11C7/06

  Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits} · CPC title

• G11C29/021

  in voltage or current generators · CPC title

• G11C29/023

  in clock generator or timing circuitry · CPC title

• G11C11/4093

  Input/output [I/O] data interface arrangements, e.g. data buffers · CPC title