Devices incorporating integrated detectors and ultra-small vertical cavity surface emitting laser emitters

Patent metadata

Field	Value
Publication number	US-11187789-B2
Application number	US-201815951884-A
Country	US
Kind code	B2
Filing date	Apr 12, 2018
Priority date	Apr 12, 2017
Publication date	Nov 30, 2021
Grant date	Nov 30, 2021

Abstract

A semiconductor device includes a detector structure. The detector structure includes an integrated circuit on a substrate, and a photo detector on an upper surface of the integrated circuit that is opposite the substrate, where the substrate is non-native to the photo detector. A System-on-Chip apparatus includes at least one laser emitter on a non-native substrate, at least one photo detector on the non-native substrate, and an input/output circuit. The at least one photo detector of the second plurality of photo detectors is disposed on an integrated circuit between the at least one photo detector and the non-native substrate to form a detector structure.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a plurality of laser emitters on a substrate, wherein the substrate is non-native to the plurality of laser emitters, and wherein a spacing between adjacent ones of the laser emitters is less than 500 μm; and
a detector structure, wherein the detector structure comprises:
an integrated circuit on the substrate; and
a plurality of photo detectors on an upper surface of the integrated circuit that is opposite the substrate, wherein the substrate is non-native to the photo detector, and
wherein a ratio of a first area of the plurality of photo detectors to a second area of the detector structure is greater than 80%.

2. The semiconductor device of claim 1 , wherein the plurality of laser emitters and the detector structure are disposed on opposing surfaces of the substrate.

3. The semiconductor device of claim 2 , wherein the plurality of laser emitters are configured to emit light through the substrate.

4. The semiconductor device of claim 1 , wherein a spacing between adjacent photo detectors of the plurality of photo detectors is less than 20 μm, and
wherein the plurality of photo detectors comprises a pin, a pinFET, a linear avalanche photodiode (APD), a silicon photomultiplier (SiPM), and/or a single photon avalanche diode (SPAD) device.

5. The semiconductor device of claim 4 , wherein the plurality of photo detectors comprises a first array of photo detectors having a first density and a second array of photo detectors having a second density, different from the first density.

6. The semiconductor device of claim 1 , wherein at least one of the plurality of photo detectors comprises a broken tether portion and/or a relief feature at a periphery thereof.

7. The semiconductor device of claim 1 , further comprising a lenslet on at least one of the plurality of photo detectors.

8. A System-on-Chip apparatus comprising:
at least one laser emitter on a non-native substrate;
a plurality of photo detectors on the non-native substrate; and
an input/output circuit,
wherein the plurality of photo detectors is disposed on an integrated circuit between the plurality of photo detectors and the non-native substrate to form a detector structure,
wherein a spacing between adjacent photo detectors of the plurality of photo detectors is less than 150 μm.

9. The apparatus of claim 8 , wherein a ratio of a first area of the plurality of photo detectors to a second area of the detector structure is greater than 80%.

10. The apparatus of claim 8 , further comprising a timing control processor coupled to the at least one laser emitter, the plurality of photo detectors, and the input/output circuit.

11. The apparatus of claim 8 , wherein a surface of the non-native substrate having the at least one laser emitter and the plurality of photo detectors thereon has a width and/or a length of less than 2 millimeters.

12. The apparatus of claim 8 , wherein the input/output circuit is configured to provide a 3D point cloud based on an operation of the at least one laser emitter and the plurality of photo detectors.

13. A semiconductor device comprising:
a substrate;
at least one laser emitter on the substrate, the at least one laser emitter configured to emit light, wherein the substrate is non-native to the at least one laser emitter; and
a plurality of photo detectors on the substrate, wherein the substrate is non-native to each of the plurality of photo detectors,
wherein the plurality of photo detectors are configured to detect a portion of the light from the at least one laser emitter that is reflected from a target,
wherein each of the plurality of photo detectors is on circuitry comprising a logic layer that is between the plurality of photo detectors and the substrate, and
wherein a spacing between adjacent photo detectors of the plurality of photo detectors is less than 150 μm.

14. The semiconductor device of claim 13 , wherein the at least one laser emitter and the plurality of photo detectors are disposed on opposing surfaces of the substrate.

15. The semiconductor device of claim 14 , wherein the at least one laser emitter is configured to emit the light through the substrate.

16. The semiconductor device of claim 13 , wherein at least one of the plurality of photo detectors comprises a broken tether portion and/or a relief feature at a periphery thereof.

17. The semiconductor device of claim 13 , wherein the at least one laser emitter is adjacent at least one of the plurality of photo detectors on a same side of the substrate.

18. A semiconductor device comprising:
a substrate;
at least one laser emitter on the substrate, the at least one laser emitter configured to emit light, wherein the substrate is non-native to the at least one laser emitter; and
a plurality of photo detectors on the substrate, wherein the substrate is non-native to each of the plurality of photo detectors,
wherein the plurality of photo detectors are configured to detect a portion of the light from the at least one laser emitter that is reflected from a target,
wherein each of the plurality of photo detectors is on circuitry comprising a logic layer that is between the plurality of photo detectors and the substrate, and
wherein the at least one laser emitter is a plurality of laser emitters having a spacing between adjacent ones of the laser emitters that is less than 500 μm.

19. The semiconductor device of claim 18 , wherein the at least one laser emitter is adjacent at least one of the plurality of photo detectors on a same side of the substrate.

20. The semiconductor device of claim 18 , wherein the at least one laser emitter and the plurality of photo detectors are disposed on opposing surfaces of the substrate.

Assignees

• Sense Photonics Inc

Inventors

• Burroughs Scott
• Fisher Brent
• Carter James

Classifications

• H10W90/00

  Package configurations · CPC title

• G01S7/4815 Primary

  using multiple transmitters · CPC title

• G01J1/44 Primary

  Electric circuits {(for command of an exposure part G03B7/02)} · CPC title

• H01S5/426

  Vertically stacked cavities · CPC title

• H01S5/423

  having a vertical cavity · CPC title