Receiving end of electronic device and method of setting phase threshold of timing recovery operation

Patent metadata

Field	Value
Publication number	US-11184010-B1
Application number	US-202117355224-A
Country	US
Kind code	B1
Filing date	Jun 23, 2021
Priority date	Jun 30, 2020
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A receiving end of an electronic device includes an analog front end (AFE) circuit, a phase detector (PD), and a calculation circuit. The AFE circuit receives an input signal and adjusts the phase of the input signal according to a phase control signal. The PD detects the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculates a target phase value according to the phase difference accumulated value, and generates a first phase driving value according to the target phase value and the current phase value. The calculation circuit generates the phase control signal according to the first phase driving value and a phase threshold. After the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first and second phase driving values.

First claim

What is claimed is:

1. A receiving end of an electronic device, comprising:
an analog front end circuit configured to receive an input signal and adjust a phase of the input signal according to a phase control signal;
a phase detector coupled to the analog front end circuit and configured to detect the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculate a target phase value according to the phase difference accumulated value, and generate a first phase driving value according to the target phase value and the current phase value; and
a calculation circuit coupled to the phase detector and the analog front end circuit and configured to generate the phase control signal according to the first phase driving value and a phase threshold;
wherein after the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the first phase driving value and the second phase driving value.

2. The receiving end of the electronic device of claim 1 , wherein the calculation circuit calculates an absolute difference between the first phase driving value and the second phase driving value and multiplies the absolute difference by a multiple ratio to generate the phase threshold.

3. The receiving end of the electronic device of claim 2 , wherein the multiple ratio is one.

4. A receiving end of an electronic device, comprising:
an analog front end circuit configured to receive an input signal and adjust a phase of the input signal according to a phase control signal;
a phase detector coupled to the analog front end circuit and configured to detect the phase of the input signal to generate a current phase value and a phase difference accumulated value, calculate a target phase value according to the phase difference accumulated value, and generate a first phase driving value according to the target phase value and the current phase value; and
a calculation circuit coupled to the phase detector and the analog front end circuit and configured to generate the phase control signal according to the first phase driving value and a phase threshold;
wherein after the calculation circuit generates the phase control signal, the phase detector generates a second phase driving value, and the calculation circuit updates the phase threshold according to the phase threshold and the second phase driving value.

5. The receiving end of the electronic device of claim 4 , wherein the calculation circuit calculates an absolute difference between the phase threshold and the second phase driving value and multiplies the absolute difference by a multiple ratio to generate the phase threshold.

6. The receiving end of the electronic device of claim 5 , wherein the multiple ratio is one.

7. A method of setting a phase threshold of a timing recovery operation, comprising:
(A) receiving an input signal;
(B) detecting a phase of the input signal to generate a current phase value and a phase difference accumulated value;
(C) calculating a target phase value according to the phase difference accumulated value;
(D) generating a first phase driving value according to the target phase value and the current phase value;
(E) generating a phase control signal according to the first phase driving value and a phase threshold;
(F) adjusting the phase of the input signal according to the phase control signal;
(G) repeating steps (A) to (C) to update the target phase value and the current phase value;
(H) generating a second phase driving value according to the updated target phase value and the updated current phase value; and
(I) updating the phase threshold according to an absolute difference between the first phase driving value and the second phase driving value, or according to an absolute difference between the phase threshold and the second phase driving value.

8. The method of claim 7 , wherein step (I) multiplies the absolute difference by a multiple ratio to generate the phase threshold.

9. The method of claim 8 , wherein the multiple ratio is one.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chen Yan-Guei
• Lue Hsin-Yu
• Huang Liang-Wei
• Huang Hui-Min

Classifications

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title