Dead time generator and digital signal processing device

Patent metadata

Field	Value
Publication number	US-11183990-B2
Application number	US-201816627997-A
Country	US
Kind code	B2
Filing date	Jun 22, 2018
Priority date	Jul 28, 2017
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A clock synchronization signal generator generates a dead time in which gates of both of two switching elements included in a switching circuit are in an off state, and generates the dead time for controlling a plurality of pulses having different widths to pulses having a constant width, which is output by the switching circuit.

First claim

The invention claimed is:

1. A digital signal processing device comprising:
a first differential receiver that generates a first digital signal,
a second differential receiver that generates a clock signal,
a digital sampling circuit that samples the first digital signal supplied from the first differential receiver and converts the first digital signal into a second digital signal and a third digital signal,
a dead time generator that generates a clock synchronization signal based on the clock signal supplied from the second differential receiver,
a gate drive circuit that generates a first gate signal from the second digital signal supplied from the digital sampling circuit and the clock synchronization signal supplied from the dead time generator, and generates a second gate signal from the third digital signal supplied from the digital sampling circuit and the clock synchronization signal supplied from the dead time generator,
a switching circuit that includes two switching elements, wherein the two switching elements respectively are supplied with the first gate signal and the second gate signal from the drive circuit, wherein
the dead time generator generates a dead time in which gates of both of the two switching elements are in an off state,
the clock synchronization signal alternately repeats the dead time of a first time width and a pulse of a second time width,
the second digital signal includes at least one single pulse, each having a third time width, and at least one continuous pulse, each having a fourth time width that is twice the third time width,
the third digital signal includes at least one single pulse, each having a fifth time width, and at least one continuous pulse, each having a sixth time width that is twice the fifth time width,
the first gate signal is generated as a logical product of the clock synchronization signal and the second digital signal, and
the second gate signal is generated as a logical product of the clock synchronization signal and the third digital signal.

2. The digital signal processing device according to claim 1 ,
wherein the digital sampling circuit generates the second digital signal and the third digital signal by causing a start point of time of the first digital signal to coincide with a rising start point of time of the clock signal.

3. The digital signal processing device according to claim 1 ,
wherein the dead time generator includes a delay circuit that generates a clock delay inversion signal and generates a negative logical product of the clock signal and the clock delay inversion signal.

4. The digital signal processing device according to claim 1 ,
wherein the dead time generator includes a delay circuit that generates a clock delay signal and generates a logical sum of a clock inversion signal obtained by inverting the clock signal and the clock delay signal.

5. The digital signal processing device according to claim 1 ,
wherein the switching circuit is a half bridge circuit,
the two switching elements are a first switching element and a second switching element, one of the first switching element and the second switching element is on the high side, and the other one is on the low side,
the gate drive circuit includes a first gate drive circuit connected to the first switching element and a second gate drive circuit connected to the second switching element,
the first gate drive circuit generates the gate signal which is a logical product of the clock synchronization signal and the second digital signal,
the second gate drive circuit generates the gate signal which is a logical product of the clock synchronization signal and a digital inversion signal obtained by inverting the third digital signal,
a first drain-source voltage supplied to the first switching element includes two types of pulses having a same time width as the single pulse of the second digital signal and the continuous pulse of the second digital signal,
a second drain-source voltage supplied to the second switching element includes two types of pulses that respectively have a same time width as the single pulse of the third digital signal and a same time width as the continuous pulse of the third digital signal.

6. The digital signal processing device according to claim 1 ,
wherein the switching circuit performs resonant switching.

Assignees

• Sharp Kk

Inventors

• Nakahira Tsuyoshi
• Nishigaki Akihiro

Classifications

• H03K3/78

  Generating a single train of pulses having a predetermined pattern, e.g. a predetermined number · CPC title

• H03K3/017 Primary

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03F3/185

  with field-effect devices (H03F3/187 takes precedence) · CPC title

• H03F2200/03

  the amplifier being designed for audio applications · CPC title

• H03K5/1515

  non-overlapping · CPC title