Photoelectric detector, preparation method thereof, display panel and display device

Patent metadata

Field	Value
Publication number	US-11183610-B2
Application number	US-202016909526-A
Country	US
Kind code	B2
Filing date	Jun 23, 2020
Priority date	Jul 2, 2019
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

The present disclosure discloses a photoelectric detector, a preparation method thereof, a display panel and a display device. The photoelectric detector includes a base, and a thin film transistor (TFT) and a photosensitive PIN device on the base, wherein the PIN device includes an I-type region that does not overlap with an orthographic projection of the TFT on the base; a first etching barrier layer covering a top surface of the I-type region; a first heavily doped region in contact with a side surface on a side, proximate to the TFT, of the I-type region; and a second heavily doped region in contact with a side surface on a side, away from the TFT, of the I-type region, the doping types of the first heavily doped region and the second heavily doped region being different from each other.

First claim

What is claimed is:

1. A photoelectric detector, comprising a base, a thin film transistor (TFT) on the base, and a photosensitive PIN device on the base, wherein the PIN device comprises:
an I-type region, wherein an orthographic projection, on the base, of the I-type region does not overlap with an orthographic projection, on the base, of the TFT;
a first etching barrier layer, covering a top surface of the I-type region;
a first heavily doped region, in contact with a side surface on a side, proximate to the TFT, of the I-type region;
a second heavily doped region, in contact with a side surface on a side, away from the TFT, of the I-type region; wherein a doping type of the first heavily doped region is different from a doping type of the second heavily doped region;
a first electrode, covering a top surface of the first heavily doped region; wherein the first electrode is electrically connected to a drain of the TFT;
a second electrode, covering a top surface of the second heavily doped region; wherein the second electrode is electrically connected to an electrode lead wire; and
a second etching barrier layer, covering a top surface of the second electrode; wherein the electrode lead wire is electrically connected to the second electrode through a first via hole that runs through the second etching barrier layer.

2. The photoelectric detector according to claim 1 , wherein the PIN device further comprises:
a third etching barrier layer, covering a top surface of the first electrode; wherein a connecting wire electrically connected with the drain of the TFT is electrically connected to the first electrode through a second via hole that runs through the third etching barrier layer.

3. The photoelectric detector according to claim 2 , wherein the electrode lead wire, the connecting wire, a source of the TFT, and the drain of the TFT are in a same layer and made of a same material.

4. The photoelectric detector according to claim 3 , wherein the TFT comprises:
a buffer layer, an active layer, a gate insulating layer, a gate, an interlayer dielectric layer, the source and the drain that are successively stacked on the base; wherein the source is electrically connected to a heavily doped region at one end of the active layer through a third via hole that runs through the interlayer dielectric layer and the gate insulating layer, and the drain is electrically connected to a heavily doped region at the other end of the active layer through a fourth via hole that runs through the interlayer dielectric layer and the gate insulating layer.

5. The photoelectric detector according to claim 4 , wherein the doping type of the first heavily doped region and a doping type of heavily doped regions of the active layer of the TFT are same.

6. The photoelectric detector according to claim 5 , wherein the first heavily doped region and the first electrode extend to an area where the TFT is located to serve as the drain of the TFT.

7. The photoelectric detector according to claim 5 , wherein the electrode lead wire comprises a first lead wire portion in a same layer as the first heavily doped region and in contact with the second electrode through the first via hole, and a second lead wire portion on the first lead wire portion and in a same layer as the first electrode.

8. The photoelectric detector according to claim 6 , wherein the electrode lead wire comprises a first lead wire portion in a same layer as the first heavily doped region and in contact with the second electrode through the first via hole, and a second lead wire portion on the first lead wire portion and in a same layer as the first electrode.

9. A display panel, comprising: a display substrate and the photoelectric detector according to claim 1 , wherein a base in the display substrate and the base in the photoelectric detector are a same base.

10. A display device, comprising the display panel according to claim 9 .

11. A preparation method of the photoelectric detector according to claim 1 , comprising:
forming a buffer layer, an active layer, a gate insulating layer and a gate successively on the base;
performing ion implantation for heavy doping on the active layer to form a heavily doped region;
forming an interlayer dielectric layer on the gate;
forming an a-Si layer and a first etching barrier film successively on the interlayer dielectric layer;
patterning the a-Si layer and the first etching barrier film by a same patterning process to form the I-type region and the first etching barrier layer covering the top surface of the I-type region;
forming a second heavily doped layer, a second electrode layer and a second etching barrier film successively on the first etching barrier layer;
patterning the second heavily doped layer, the second electrode layer and the second etching barrier film by a same patterning process to form the second heavily doped region, the second electrode and a second etching barrier layer stacked successively on the side, away from the TFT, of the I-type region;
forming a first heavily doped layer and a first electrode layer successively on the second etching barrier layer;
patterning the first heavily doped layer and the first electrode layer by a same patterning process to form the first heavily doped region and the first electrode stacked successively on the side, proximate to the TFT, of the I-type region; and
forming a source, and the drain electrically connected to the first electrode on the interlayer dielectric layer, and forming the electrode lead wire electrically connected to the second electrode on the second etching barrier layer while forming the source and the drain.

12. The preparation method according to claim 11 , further comprising:
forming a third etching barrier film on the first electrode layer; and
patterning the first heavily doped layer, the first electrode layer and the third etching barrier film by a same patterning process to form the first heavily doped region, the first electrode and the third etching barrier layer stacked successively on the side, proximate to the TFT, of the I-type region.

13. The preparation method according to claim 12 , further comprising:
patterning the second etching barrier layer, the third etching barrier layer, the interlayer dielectric layer and the gate insulating layer by a same patterning process to form a first via hole running through the second etching barrier layer, a second via hole running through the third etching barrier layer, and a third via hole and a fourth via hole running through the interlayer dielectric layer and the gate insulating layer, before forming the source, and the drain electrically connected to the first electrode on the interlayer dielectric layer.

14. The manufacturing method according to claim 11 , further comprising:
patterning the second etching barrier layer, the interlayer dielectric layer and the gate insulating layer by a same patterning process to form a first via hole running through the second etching barrier layer, and a third via hole and a fourth via hole running through the interlayer dielectric layer and the gate insulating layer, before forming a first heavily doped layer and a first electrode layer successively on the second etching barrier layer.

15. The preparation method according to claim 14 , wherein the forming the source, and the drain electrically connected to the first electrode on the interlayer dielectric layer, and forming an electrode lead wire electrically connected to the second electrode on the second etching barrier layer while forming the source and the drain comprises:
patterning the first

Assignees

• Boe Technology Group Co Ltd

Inventors

• Li Chao
• Du Jianhua
• Guan Feng
• Gao Yupeng
• Qiang Zhaohui
• Wang Zhi
• Lyu Yang
• Luo Chao

Classifications

• H10D86/60

  wherein the TFTs are in active matrices · CPC title

• H10D86/40

  characterised by multiple TFTs · CPC title

• H10F71/00

  Manufacture or treatment of devices covered by this subclass (patterning processes to connect thin photovoltaic cells in integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/33; manufacture or treatment of encapsulations or containers for integrated devices, or assemblies of multiple devices, having photovoltaic cells H10F19/80; manufacture or treatment of integrated devices, or assemblies of multiple devices, comprising at least one element in which radiation controls the flow of current H10F39/00) · CPC title

• H10F55/00

  Radiation-sensitive semiconductor devices covered by groups H10F10/00, H10F19/00 or H10F30/00 being structurally associated with electric light sources and electrically or optically coupled thereto · CPC title

• H10F30/223 Primary

  the potential barrier being a PIN barrier · CPC title