Flip-chip package substrate and method for fabricating the same

Patent metadata

Field	Value
Publication number	US-11183447-B2
Application number	US-202017020984-A
Country	US
Kind code	B2
Filing date	Sep 15, 2020
Priority date	Sep 27, 2019
Publication date	Nov 23, 2021
Grant date	Nov 23, 2021

Abstract

A flip-chip package substrate and a method for fabricating the same are provided. An insulation layer is formed on two opposing sides of a middle layer to form a composite core structure and increase the rigidity of the flip-chip package substrate. Therefore, the core structure can be made thinner. The conductive structures can also have a smaller end size, and more conductive points can be disposed within a unit area. Therefore, a circuit structure can be produced that have a fine line pitch and a high wiring density, satisfy the packaging demands of highly integrated circuit/large size substrate, and avoid an electronic package from being warpage.

First claim

What is claimed is:

1. A flip-chip package substrate, comprising: a core structure having a first side, and a second side opposing the first side, and comprising a middle layer, and two insulation layers respectively bonded to two opposing sides of the middle layer and made of a different material from the middle layer; a plurality of conductive structures, each of which penetrating the middle layer and the insulation layers and being exposed from the first and second sides of the core structure; a circuit structure formed on the first and second sides of the core structure in a dual-side built-up circuit manner and electrically connected to the conductive structures; and a strengthening structure disposed on the circuit structure on at least one of the first side and the second side of the core structure, wherein the strengthening structure comprises a rigid portion and an insulation portion bonding the rigid portion onto the circuit structure.

2. The flip-chip package substrate of claim 1 , wherein the middle layer of the core structure is made of an insulative material containing glass fiber.

3. The flip-chip package substrate of claim 2 , wherein the insulative material is highly rigid Bismaleimide Triazine (BT) or flame retardant (FR-5).

4. The flip-chip package substrate of claim 1 , wherein the insulation layer of the core structure is made of a highly rigid dielectric material.

5. The flip-chip package substrate of claim 4 , wherein the highly rigid dielectric material is epoxy resin or Ajinomoto Build-up Film (ABF).

6. A method for fabricating a flip-chip package substrate, comprising: providing a middle layer; bonding an insulation layer onto two opposing sides of the middle layer, respectively, allowing the middle layer and the insulation layer to act as a core structure that has a first side and a second side opposing the first side, wherein the middle layer is made of a different material from the insulation layer; forming in the core structure a plurality of conductive structures, each of which penetrating the middle layer and the insulation layer and being exposed from the first and second sides of the core structure; forming on the first and second sides of the core structure a circuit structure in a dual-side built-up circuit manner, and electrically connecting the circuit structure to the conductive structures; and forming a strengthening structure on the circuit structure on at least one of the first side and the second side of the core structure, wherein the strengthening structure comprises a rigid portion and an insulation portion bonding the rigid portion onto the circuit structure.

7. The method of claim 6 , wherein the middle layer of the core structure is made of an insulative material containing glass fiber.

8. The method of claim 7 , wherein the insulative material is highly rigid Bismaleimide Triazine (BT) or flame retardant (FR-5).

9. The method of claim 6 , wherein the insulation layer of the core structure is made of a highly rigid dielectric material.

10. The method of claim 9 , wherein the highly rigid dielectric material is epoxy resin or Ajinomoto Build-up Film (ABF).

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Chou Pao-Hung
• Yu Chun-Hsien
• Hsu Shih-Ping

Classifications

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/635 Primary

  Through-vias · CPC title

• H10W70/095

  of vias therein · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W70/65 Primary

  Shapes or dispositions of interconnections · CPC title