Overvoltage protection circuit

US11177650B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11177650-B2
Application numberUS-201916536825-A
CountryUS
Kind codeB2
Filing dateAug 9, 2019
Priority dateAug 9, 2019
Publication dateNov 16, 2021
Grant dateNov 16, 2021

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An overvoltage protection circuit includes an input terminal, an output terminal, a clamp transistor, and a selector circuit. The clamp transistor is configured to control current flow between the input terminal and the output terminal. The clamp transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal. The selector circuit is configured to control a resistance of the clamp transistor based on a voltage at the input terminal. The selector circuit includes a first terminal coupled to the first terminal of the clamp transistor, a second terminal coupled to the second terminal of the clamp transistor, and a third terminal coupled to a third terminal of the clamp transistor.

First claim

Opening claim text (preview).

What is claimed is: 1. An amplifier circuit comprising: a signal input terminal; an amplifier; and an overvoltage protection circuit coupled to the signal input terminal and an input of the amplifier, and comprising: a first transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the input of the amplifier; a second transistor comprising: a first terminal coupled to the signal input terminal; a second terminal coupled to a third terminal of the first transistor; and a third terminal coupled to the third terminal of the first transistor; a third transistor comprising: a first terminal coupled to the third terminal of the first transistor; a second terminal coupled to the input of the amplifier; and a third terminal coupled to the third terminal of the first transistor; wherein the overvoltage protection circuit further comprises: a fourth transistor comprising: a first terminal coupled to the second terminal of the first transistor; and a second terminal coupled to the input of the amplifier; wherein the overvoltage protection circuit further comprises: a fifth transistor comprising: a first terminal coupled to the second terminal of the first transistor; a second terminal coupled to a third terminal of the fourth transistor; and a third terminal coupled to the third terminal of the fourth transistor. 2. An amplifier circuit comprising: a signal input terminal; an amplifier; and an overvoltage protection circuit coupled to the signal input terminal and an input of the amplifier, and comprising: a first transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the input of the amplifier; a second transistor comprising: a first terminal coupled to the signal input terminal; a second terminal coupled to a third terminal of the first transistor; and a third terminal coupled to the third terminal of the first transistor; a third transistor comprising: a first terminal coupled to the third terminal of the first transistor; a second terminal coupled to the input of the amplifier; and a third terminal coupled to the third terminal of the first transistor; wherein the overvoltage protection circuit further comprises: a fourth transistor comprising: a first terminal coupled to the second terminal of the first transistor; and a second terminal coupled to the input of the amplifier; wherein the overvoltage protection circuit further comprises: a fifth transistor comprising: a first terminal coupled to a third terminal of the fourth transistor; a second terminal coupled to the input of the amplifier; and a third terminal coupled to the third terminal of the fourth transistor. 3. An amplifier circuit comprising: a signal input terminal; an amplifier; and an overvoltage protection circuit coupled to the signal input terminal and an input of the amplifier, and comprising: a first transistor comprising: a first terminal coupled to the signal input terminal; and a second terminal coupled to the input of the amplifier; a second transistor comprising: a first terminal coupled to the signal input terminal; a second terminal coupled to a third terminal of the first transistor; and a third terminal coupled to the third terminal of the first transistor; a third transistor comprising: a first terminal coupled to the third terminal of the first transistor; a second terminal coupled to the input of the amplifier; and a third terminal coupled to the third terminal of the first transistor; wherein: the signal input terminal is a first signal input terminal; the amplifier circuit comprises a second signal input terminal; the input is a first input; the amplifier comprises a second input; the overvoltage protection circuit is a first overvoltage protection circuit; and the amplifier circuit comprises a second overvoltage protection circuit coupled to the second signal input terminal and the second input, and comprising: a fourth transistor comprising: a first terminal coupled to the second signal input terminal; and a second terminal coupled to the second input of the amplifier; a fifth transistor comprising: a first terminal coupled to the second signal input terminal; a second terminal coupled to a third terminal of the fourth transistor; and a third terminal coupled to the third terminal of the fourth transistor; a sixth transistor comprising: a first terminal coupled to the third terminal of the fourth transistor; a second terminal coupled to the second input of the amplifier; and a third terminal coupled to the third terminal of the fourth transistor. 4. The amplifier circuit of claim 3 , wherein the second overvoltage protection circuit further comprises: a seventh transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; and a second terminal coupled to the second input of the amplifier; an eighth transistor comprising: a first terminal coupled to the second terminal of the fourth transistor; a second terminal coupled to a third terminal of the seventh transistor; and a third terminal coupled to the third terminal of the seventh transistor; and a ninth transistor comprising: a first terminal coupled to a third terminal of the seventh transistor; a second terminal coupled to the second input of the amplifier; and a third terminal coupled to the third terminal of the seventh transistor. 5. An overvoltage protection circuit, comprising: an input terminal; an output terminal; a first transistor comprising: a first terminal coupled to the input terminal; and a second terminal coupled to the output terminal; a second transistor comprising: a first terminal coupled to the input terminal; a second terminal coupled to a third terminal of the first transistor; and a third terminal coupled to the third terminal of the first transistor; a third transistor comprising: a first terminal coupled to the third terminal of the first transistor; a second terminal coupled to the output terminal; a third terminal coupled to the third terminal of the first transistor; a fourth transistor comprising: a first terminal coupled to the second terminal of the first transistor; and a second terminal coupled to the output terminal; and a fifth transistor comprising: a first terminal coupled to the second terminal of the first transistor; a second terminal coupled to a third terminal of the fourth transistor; and a third terminal coupled to the third terminal of the fourth transistor. 6. An overvoltage protection circuit, comprising: an input terminal; an output terminal; a first transistor comprising: a first terminal coupled to the input terminal; and a second terminal coupled to the output terminal; a second transistor comprising: a first terminal coupled to the input terminal; a second terminal coupled to a third terminal of the first transistor; and a third terminal coupled to the third terminal of the first transistor; a third transistor comprising: a first terminal coupled to the third terminal of the first transistor; a second terminal coupled to the output terminal; a third terminal coupled to the third terminal of the first transistor; a fourth transistor comprising: a first terminal coupled to the second terminal of the first transistor; and a second terminal coupled to the output terminal; and a fifth transistor comprising: a first terminal coupled to a third terminal of the fourth transistor; a second terminal coupled to the output terminal; and a third terminal coupled to the third terminal of the fourth transistor.

Assignees

Inventors

Classifications

  • in connection with live-insertion of plug-in units (involving communication with a central processing unit G06F13/40) · CPC title

  • using IC blocks as the active amplifying circuit · CPC title

  • with field-effect devices · CPC title

  • H02H9/04Primary

    responsive to excess voltage (lightning arrestors H01C7/12, H01C8/04, H01G9/18, H01T) · CPC title

  • the IC comprising one or more diodes as shunt to the input leads · CPC title

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Frequently asked questions

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What does patent US11177650B2 cover?
An overvoltage protection circuit includes an input terminal, an output terminal, a clamp transistor, and a selector circuit. The clamp transistor is configured to control current flow between the input terminal and the output terminal. The clamp transistor includes a first terminal coupled to the input terminal, a second terminal coupled to the output terminal. The selector circuit is configur…
Who is the assignee on this patent?
Texas Instruments Inc
What technology area does this patent fall under?
Primary CPC classification H03F3/45475. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 16 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).