III-N epitaxial device structures on free standing silicon mesas

Patent metadata

Field	Value
Publication number	US-11177376-B2
Application number	US-201916258422-A
Country	US
Kind code	B2
Filing date	Jan 25, 2019
Priority date	Sep 25, 2014
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a mesa over a substrate comprising a first crystal, the first crystal comprising silicon, the mesa having a top surface at a first z-height from a bottom of the mesa;
a second crystal comprising a first III-N material, the second crystal over the top surface of the mesa with a c-axis of the second crystal substantially orthogonal to the top surface, the second crystal comprising a peripheral region that extends laterally beyond a sidewall of the mesa;
a second III-N material over the first III-N material, the second III-N material having a composition different from a composition of the first III-N material; and
a monocrystalline material comprising silicon on the substrate and adjacent to the mesa, wherein the monocrystalline material has a second z-height, relative to the bottom of the mesa, that is greater than the first z-height.

2. The semiconductor device structure of claim 1 , wherein the second III-N material is over at least one of a (0001) or a (000−1) surface of the first III-N material.

3. The semiconductor device structure of claim 2 , wherein the second crystal has a sidewall surface with an m-plane and the second III-N material is over both a (0001) and a (000−1) surface of the first III-N material.

4. The semiconductor device structure of claim 1 , wherein:
the first z-height is at least 500 nm;
the second crystal has a maximum z-thickness over the top surface that is no more than 500 nm; and
the peripheral region extends laterally beyond the sidewall by at least 500 μm.

5. The semiconductor device structure of claim 4 , wherein:
a minimum lateral width of the mesa is between 500 μm and 1 μm;
the first z-height is between 750 μm and 5 μm; and
a third III-N material is over the second III-N material, the third III-N material having a composition sufficiently distinct from that of the second III-N material to maintain a two-dimensional electron gas (2DEG) within the third III-N material.

6. The semiconductor device structure of claim 1 , wherein:
the second crystal has a sidewall with an m-plane; and
the second III-N material is over the m-plane.

7. The semiconductor device structure of claim 1 , wherein:
a core portion of the second crystal over the top surface of the mesa has a first density of threading dislocations extending from the top surface of the mesa through a z-height of the second crystal; and
the peripheral region has a second density of threading dislocations that is at least an order of magnitude lower than the first density of threading dislocations.

8. The semiconductor device structure of claim 7 , wherein:
the mesa has a lateral width proximal to the second crystal, the lateral width being smaller than that of the core portion of the second crystal; and
an exposed region of the core portion of the second crystal is substantially free of the second 111-N material.

9. The semiconductor device structure of claim 1 , wherein:
the first III-N material comprises predominantly Ga and N with a c-plane no more than 10° from parallel to a (100) plane of the substrate; and
the second III-N material comprises more Al than the first III-N material.

10. A semiconductor device, comprising:
a semiconductor structure including:
a mesa comprising a first crystal, the first crystal comprising silicon;
a second crystal comprising a first III-N material, the second crystal over a top surface of the mesa with a c-axis of the second crystal substantially orthogonal to the top surface, the second crystal comprising a peripheral region that extends laterally beyond a sidewall of the mesa; and
a second III-N material over the first material, the second III-N material having a composition different than that of the first material; and

one or more device terminals coupled to the semiconductor structure, wherein the one or more device terminals further comprise a gate terminal disposed between a source terminal and a drain terminal, at least the gate terminal located within the peripheral region.

11. The device of claim 10 , wherein:
the second III-N material comprises a two-dimensional electron gas (2DEG) in at least a portion of the peripheral region; and
the gate terminal is to modulate the 2DEG.

12. The device of claim 11 , wherein:
the second III-N material is over a (0001) surface of the second crystal and over a (000−1) surface of the second crystal;
a third III-N material is over a (000−1) surface of the second III-N material, the third III-N material comprising a second 2DEG within the third III-N material; and
the one or more device terminals further comprise a second gate terminal between a second source terminal and a second drain terminal, at least the second gate terminal located within the peripheral region to modulate the second 2DEG.

13. The semiconductor device structure of claim 1 , wherein:
the second III-N material is a layer of a light emitting diode (LED) stack, the LED stack covering at least one of a (0001) or a (000−1) surface of the peripheral region.

Assignees

• Intel Corp

Inventors

• Dasgupta Sansaptak
• Then Han Wui
• Gardner Sanaz K
• Radosavljevic Marko
• Sung Seung Hoon
• Chu-Kung Benjamin
• Chau Robert S

Classifications

• H10P14/3416

  Nitrides · CPC title

• H10P14/2926

  Crystal orientations · CPC title

• H10P14/2925

  Surface structures · CPC title

• H10P14/2905

  Silicon, silicon germanium or germanium · CPC title

• H10P14/278

  Pendeoepitaxy · CPC title