Computational random access memory (CRAM) based on spin-orbit torque devices

Patent metadata

Field	Value
Publication number	US-11176979-B2
Application number	US-202016803454-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Feb 28, 2019
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A logic-memory cell includes a spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals is capable of changing a resistance between the first and second terminals. In the cell, a first transistor is connected between a logic connection line and the first terminal of the spin-orbit torque device and a second transistor is connected between the logic connection line and the third terminal of the spin-orbit torque device.

First claim

What is claimed is:

1. A plurality of logic-memory cells comprising:
a first logic-memory cell comprising:
a first spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals of the first spin-orbit torque device is capable of changing a resistance between the first and second terminals of the first spin-orbit torque device, the second terminal of the first spin-orbit torque device connected to a first select line;
a first transistor connected between a logic connection line and the first terminal of the first spin-orbit torque device; and
a second transistor connected between the logic connection line and the third terminal of the first spin-orbit torque device; and

a second logic-memory cell comprising:
a second spin-orbit torque device having first, second and third terminals configured such that current between the second and third terminals of the second spin-orbit torque device is capable of changing a resistance between the first and second terminals of the second spin-orbit torque device, the second terminal of the second spin-orbit torque device connected to a second select line;
a third transistor connected between the logic connection line and the first terminal of the second spin-orbit torque device; and
a fourth transistor connected between the logic connection line and the third terminal of the second spin-orbit torque device.

2. The plurality of logic-memory cells of claim 1 wherein current passes through the first transistor when a read operation is performed on the first logic-memory cell.

3. The plurality of logic-memory cells of claim 2 wherein current passes through the second transistor when a write operation is performed on the first logic-memory cell.

4. The plurality of logic-memory cells of claim 1 wherein the first spin-orbit torque device comprises a magnetic tunnel junction and a spin-orbit torque channel.

5. The plurality of logic-memory cells of claim 4 wherein the second and third terminal are connected to opposing ends of the spin-orbit torque channel.

6. The plurality of logic-memory cells of claim 5 wherein the magnetic tunnel junction is located between the first terminal of the first spin-orbit torque device and the spin-orbit torque channel.

7. The plurality of logic-memory cells of claim 1 wherein current between the second and third terminals of the first spin-orbit torque device in a first direction is capable of increasing the resistance between the first and second terminals of the first spin-orbit torque device and current between the second and third terminals of the first spin-orbit torque device in a second direction is capable of decreasing the resistance between the first and second terminals of the first spin-orbit torque device.

8. A cell array comprising:
a plurality of cells comprising a first subset of cells and a second subset of cells;
a logic connection line connected to each cell in the plurality of cells;
a first select line connected to each cell in the first subset of cells;
a second select line connected to each cell in the second subset of cells;
a plurality of write lines, each write line connected to a respective cell in the plurality of cells; and
a plurality of read lines, each read line connected to a respective cell in the plurality of cells;
wherein during a logic operation, at least one of the plurality of read lines is used to connect at least one respective cell of the first subset of cells to the logic connection line to provide at least one respective input value for the logic operation and one of the plurality of write lines is used to connect a respective cell of the second subset of cells to the logic connection line to produce and store an output value for the logic operation.

9. The cell array of claim 8 wherein during the logic operation a voltage is applied between the first select line and the second select line.

10. The cell array of claim 8 wherein each cell comprises a spin-orbit torque device.

11. The cell array of claim 10 wherein each spin-orbit torque device comprises a magnetic tunnel junction and a spin-orbit torque channel wherein the respective read line for each cell controls current through the magnetic tunnel junction and the respective write line for each cell controls current through the spin-orbit torque channel.

12. The cell array of claim 8 further comprising:
a second plurality of cells;
a second logic connection line connected to each cell in the second plurality of cells;
wherein each write line is connected to a respective cell in the second plurality of cells and each read line is connected to a respective cell in the second plurality of cells.

13. The cell array of claim 12 further comprising a switching transistor connected between the logic connection line and the second logic connection line such that current flows from the logic connection line through the switching transistor to the second logic connection line.

14. The cell array of claim 13 wherein during a second logic operation a cell in the plurality of cells provides an input value for the second logic operation and a cell in the second plurality of cells produces and stores an output value for the second logic operation.

15. A method comprising:
setting a read line of a first cell and a write line of a second cell to cause current to pass through a magnetic tunnel junction of the first cell, through a logic connection line connecting the first cell and the second cell and through a spin-orbit torque channel of the second cell so as to execute a logic operation and store an output of the logic operation in the second cell.

16. The method of claim 15 wherein the second cell further comprises a second magnetic tunnel junction and the output of the logic operation is stored in the second magnetic tunnel junction.

17. The method of claim 16 wherein the first cell further comprises a spin-orbit torque channel and wherein the method further comprises before setting the read line of the first cell, setting a write line of the first cell to cause current to pass through the spin-orbit torque channel of the first cell to thereby store an input value for the logic operation in the magnetic tunnel junction of the first cell.

18. The method of claim 15 further comprising:
setting a read line of a third cell to cause current to pass through a magnetic tunnel junction of the third cell, through the logic connection line connecting the third cell and the second cell and through the spin-orbit torque channel of the second cell so as to execute the logic operation and store the output of the logic operation in the second cell.

19. The method of claim 18 wherein causing current to pass through the magnetic tunnel junctions of the first and third cell, the logic connection line and the spin-orbit torque channel of the second cell comprises applying a voltage between a first select line connected to the first and third cell and a second select line connected to the second cell.

20. A pattern matching system implemented in a cell array, wherein each cell in the cell array comprises spin-orbit torque device wherein current along a first path through the cell sets a resistance along a second path through the cell, the pattern matching system comparing a pattern to multiple references in parallel using the cell array.

21. A cell array that receives power from an energy harvesting system wherein each cell in the cell array comprises a spin-orbit torqu

Assignees

• Univ Minnesota

Inventors

• Wang Jian-Ping
• Sapatnekar Sachin S
• Karpuzcu Ulya R
• Zhao Zhengyang
• Zabihi Masoud
• Resch Michael Salonik
• Chowdhury Zamshed I
• Peterson Thomas

Classifications

• G11C11/18

  using Hall-effect devices · CPC title

• G11C11/161 Primary

  details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell · CPC title

• G11C13/0019

  comprising bio-molecules · CPC title

• G11C11/1659

  Cell access · CPC title

• G11C11/1675

  Writing or programming circuits or methods · CPC title