Device, system and process for redundant processor error detection

Patent metadata

Field	Value
Publication number	US-11176012-B2
Application number	US-202016823180-A
Country	US
Kind code	B2
Filing date	Mar 18, 2020
Priority date	Mar 29, 2018
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

Briefly, example methods, apparatuses, and/or articles of manufacture are disclosed that may be implemented, in whole or in part, to determine indicators of potential errors in a multi-processing core lockstep computing device comprising a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores. A built-in self-test (BIST) procedure may then be based, at least in part, on the determining indicators.

First claim

What is claimed is:

1. A method comprising:
determining one or more indicators of one or more potential errors in a multi-core lockstep computing device comprising a plurality of processing cores based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores, wherein the one or more indicators indicate at least locations of the one or more potential errors in the at least two processing cores, and one or more likelihood scores associated with locations of the potential errors; and
executing a built-in self-test (BIST) procedure comprising probing testable units in an order based, at least in part, on the determined one or more indicators.

2. The method of claim 1 , wherein the one or more indicators further indicate types of errors as soft errors or hard errors.

3. The method of claim 1 , wherein the testable units are defined, at least in part, by a physical location or logical function, or a combination thereof.

4. The method of claim 1 , wherein determining the one or more indicators of the one or more potential errors further comprises:
for at least one of the at least two processing cores, associating observations of output signals generated by the at least one processing core with two or more signal categories;
in at least one of the two or more signal categories, determining divergences of observations of output signals between or among the two or more processing cores; and
determining one or more likelihood scores for at least two of the testable units based, at least in part, on the determined divergences of observations of output signals between or among the two or more processing cores.

5. The method of claim 4 , wherein the executing the BIST procedure further comprises:
determining the order based, at least in part, on the determined one or more likelihood scores.

6. The method of claim 1 , wherein the observations of output signals comprise multiple data bits, address bits or control bits, or a combination thereof.

7. An article comprising:
a non-transitory memory device comprising processor-readable instructions stored thereon which are executable by one or more processors to:
determine one or more indicators of one or more potential errors in a multi-core lockstep computing device, the multi-core lockstep computing device to comprise a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores, wherein the one or more indicators to indicate at least locations of the one or more potential errors in the at least two processing cores, and one or more likelihood scores associated with locations of the potential errors; and
execute a built-in self-test (BIST) procedure based, at least in part, on the determined one or more indicators.

8. The article of claim 7 , wherein the one or more indicators further indicate types of errors as soft errors or hard errors.

9. The article of claim 7 , wherein the multi-core lockstep computing device is segmented into testable units, and wherein execution of the built-in self-test procedure further comprises determination of an order of probing the testable units based, at least in part, on the indicators.

10. The article of claim 9 , wherein the testable units are defined, at least in part, by a physical location or logical function, or a combination thereof.

11. The article of claim 9 , wherein determination of the one or more indicators of the one or more potential errors further comprises:
for at least one of the at least two processing cores, determination of an association of observations of output signals generated by the at least one processing core with two or more signal categories;
in at least one of the two or more signal categories, determination of divergences of observations of output signals between or among the two or more processing cores; and
determination of one or more likelihood scores for at least two of the testable units based, at least in part, on the determined divergences of observations of output signals between or among the two or more processing cores.

12. The article of claim 7 , wherein the observations of output signals comprise multiple data bits, address bits or control bits, or a combination thereof.

13. An article comprising:
a non-transitory memory device comprising processor-readable instructions stored thereon which are executable by one or more processors to:
determine one or more indicators of one or more potential errors in a multi-core lockstep computing device, the multi-core lockstep computing device to comprise a plurality of processing cores, based, at least in part, on observations of output signals generated by at least two processing cores of the plurality of processing cores, wherein the multi-core lockstep computing device is segmented into testable units, and wherein execution of the built-in self-test procedure further to comprise determination of an order to probe the testable units based, at least in part, on the one or more indicators; and
execute a built-in self-test (BIST) procedure to comprise a probe of the testable units in an order based, at least in part, on the determined one or more indicators.

14. The article of claim 3 , wherein the one or more indicators further indicate types of errors as soft errors or hard errors.

15. The article of claim 3 , wherein the testable units are defined, at least in part, by a physical location or logical function, or a combination thereof.

16. The article of claim 3 , wherein determination of the one or more indicators of the one or more potential errors further comprises:
for at least one of the at least two processing cores, determination of an association of observations of output signals generated by the at least one processing core with two or more signal categories;
in at least one of the two or more signal categories, determination of divergences of observations of output signals between or among the two or more processing cores; and
determination of one or more likelihood scores for at least two of the testable units based, at least in part, on the determined divergences of observations of output signals between or among the two or more processing cores.

17. The article of claim 3 , wherein the observations of output signals comprise multiple data bits, address bits or control bits, or a combination thereof.

Assignees

• Advanced Risc Mach Ltd

Inventors

• Ozer Emre
• Iturbe Xabier
• VENU Balaji

Classifications

• G06F11/1641 Primary

  where the comparison is not performed by the redundant processing components · CPC title

• G06F11/27 Primary

  Built-in tests · CPC title

• G06F11/2236

  to test CPU or processors · CPC title