Bonding process for forming semiconductor device structure

Patent metadata

Field	Value
Publication number	US-11174156-B2
Application number	US-202016829196-A
Country	US
Kind code	B2
Filing date	Mar 25, 2020
Priority date	Nov 29, 2017
Publication date	Nov 16, 2021
Grant date	Nov 16, 2021

Abstract

A semiconductor device structure is provided. The semiconductor device structure includes a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas. A plurality of recesses are disposed in the first face of the first wafer. A first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas. A second wafer is bonded to the second face of the first wafer.

First claim

What is claimed is:

1. A semiconductor device structure, comprising:
a first wafer comprising a first face and a second face opposite the first face and having a plurality of predetermined die areas;
a plurality of recesses in the first face of the first wafer, wherein a first recess of the plurality of recesses extends in a direction substantially parallel to a first edge of at least one of the plurality of predetermined die areas and laterally surrounds the at least one of the plurality of predetermined die areas; and
a second wafer bonded to the second face of the first wafer.

2. The semiconductor device structure of claim 1 , further comprising:
a second recess in the first wafer, wherein the second recess extends along a second edge of the at least one of the plurality of predetermined die areas.

3. The semiconductor device structure of claim 2 , wherein the first recess and the second recess perpendicular intersect one another.

4. The semiconductor device structure of claim 1 , wherein the first recess continuously surrounds only one of the plurality of predetermined die areas.

5. The semiconductor device structure of claim 1 , wherein the first recess extends across a predetermined scribe line between two of the plurality of predetermined die areas.

6. The semiconductor device structure of claim 1 , wherein the first recess continuously surrounds two or more of the plurality of predetermined die areas.

7. The semiconductor device structure of claim 1 , further comprising:
a second recess in the first wafer, wherein the second recess and the first recess are positioned in a same predetermined scribe line.

8. The semiconductor device structure of claim 1 , wherein the first recess extends along predetermined scribe lines of the first wafer.

9. The semiconductor device structure of claim 1 , further comprising a plurality of movable elements on the first wafer.

10. The semiconductor device structure of claim 1 , wherein the first recess extends across one of the plurality of predetermined die areas.

11. A semiconductor device structure, comprising:
a first wafer including a plurality of predetermined die areas, the first wafer having a first face and a second face opposite the first face, wherein the plurality of predetermined die areas are spaced apart from each other by a plurality of predetermined scribe lines;
a second wafer bonded to the first face of the first wafer; and
a plurality of recesses disposed on the second face of the first wafer, wherein some of the plurality of recesses correspond to predetermined scribe lines such that a first recess of the plurality of recesses continuously surrounds two or more of the plurality of predetermined die areas.

12. The semiconductor device structure of claim 11 , wherein one of the recesses extends across one of the predetermined scribe lines.

13. The semiconductor device structure of claim 11 , wherein the first wafer does not comprise any transistor, and the second wafer is a CMOS wafer.

14. The semiconductor device structure of claim 13 , wherein the first wafer comprises a plurality of movable elements.

15. The semiconductor device structure of claim 11 , wherein one of the plurality of recesses continuously surrounds two or more of the predetermined die areas.

16. The semiconductor device structure of claim 11 , wherein the plurality of recesses comprises:
a first linear recess that extends in parallel with a first predetermined scribe line; and
a second linear recess that extends in parallel with a second predetermined scribe line such that the second linear recess perpendicularly intersects the first linear recess over one of the predetermined die areas.

17. A semiconductor device structure, comprising:
a first substrate corresponding to a first die, and comprising a first face and a second face opposite the first face;
a second substrate corresponding to a second die and bonded to the first face of the first substrate such that the second face of the first substrate faces the second substrate; and
one or more recesses in the second face of the first substrate.

18. The semiconductor device structure of claim 17 , wherein the one or more recesses includes a first recess that extends continuously and linearly from a first outer edge of the first face to a second outer edge of the first face, the second outer edge being opposite the first outer edge.

19. The semiconductor device structure of claim 18 , further comprising: a second recess that extends continuously and linearly from a third outer edge of the first face to a fourth outer edge of the first face, the third outer edge being opposite the fourth outer edge such that the second recess perpendicularly intersects the first recess.

20. The semiconductor device structure of claim 17 , wherein the one or more recesses comprises:
a first linear recess that extends in parallel with a first set of edges of the first substrate; and
a second linear recess that extends in parallel with a second set of edges of the first substrate such that the second linear recess perpendicularly intersects the first linear recess over the first die or over the second die.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chang Chih-Hang
• Wang I-Shi
• Liu Jen-Hao

Classifications

• B81C1/00269

  Bonding of solid lids or wafers to the substrate · CPC title

• B81C1/00888 Primary

  Multistep processes involving only mechanical separation, e.g. grooving followed by cleaving · CPC title

• B81C1/00238 Primary

  Joining a substrate with an electronic processing unit and a substrate with a micromechanical structure · CPC title

• B81C2201/0146

  Processes for removing material not provided for in B81C2201/0129 - B81C2201/0145 · CPC title

• B81C2201/0143

  Focussed beam, i.e. laser, ion or e-beam · CPC title