Pause communication from I/O devices supporting page faults

Patent metadata

Field	Value
Publication number	US-11169929-B2
Application number	US-201815958591-A
Country	US
Kind code	B2
Filing date	Apr 20, 2018
Priority date	Apr 20, 2018
Publication date	Nov 9, 2021
Grant date	Nov 9, 2021

Abstract

A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.

First claim

What is claimed is:

1. A processing device comprising:
a core to execute instructions; and
memory management circuitry coupled to memory, the core, and an input/output (I/O) device that supports page faults, the memory management circuitry comprising:
page translation permission circuitry to modify permissions of page translation responses to generate modified permissions in response to receiving, from the memory to the memory management circuitry, a command to pause communication between the I/O device and the memory, wherein the command to pause communication between the I/O device and the memory is transmitted based on memory consumption or bandwidth congestion; and
express invalidations circuitry to transmit, to the I/O device, an invalidation request to cause cached page translations in the I/O device to be invalidated in response to the command to pause the communication between the I/O device and the memory.

2. The processing device of claim 1 , wherein the page translation permission circuitry is further to transmit a translation response comprising the modified permissions to the I/O device in response to a translation request being received by the memory management circuitry from the I/O device.

3. The processing device of claim 2 , wherein the memory management circuitry is further to:
forgo transmitting a response to a page fault request from the I/O device, the page fault request being transmitted by the I/O device in response to the translation response.

4. The processing device of claim 1 , wherein the memory management circuitry is further to:
receive a command to exit the pause of the communication between the I/O device and the memory.

5. The processing device of claim 4 , wherein the memory management circuitry is further to:
in response to receiving the command to exit the pause of the communication, transmit requested page translations to the I/O device.

6. The processing device of claim 4 , wherein the memory management circuitry is further to:
in response to receiving the command to exit the pause of the communication, transmit a response to a page fault request from the I/O device.

7. The processing device of claim 4 , wherein the memory management circuitry receives the command to exit the pause of the communication from system software.

8. A processing system comprising:
memory; and
a processing device comprising:
a core to execute instructions; and
memory management circuitry coupled to the memory, the core, and an input/output (I/O) device that supports page faults, the memory management circuitry comprising:
page translation permission circuitry to modify permissions of page translations responses to generate modified permissions in response to receiving from the memory to the memory management circuitry, a command to pause communication between the I/O device and the memory, wherein the command to pause communication between the I/O device and the memory is transmitted based on memory consumption or bandwidth congestion; and
express invalidations circuitry to transmit, to the I/O device, an invalidation request to cause cached page translations in the I/O device to be invalidated in response to the command to pause the communication between the I/O device and the memory.

9. The processing system of claim 8 , wherein the page translation permission circuitry is further to transmit a translation response comprising the modified permissions to the I/O device in response to a translation request being received by the memory management circuitry from the I/O device.

10. The processing system of claim 9 , wherein the memory management circuitry is further to:
forgo transmitting a response to a page fault request from the I/O device, the page fault request being transmitted by the I/O device in response to the translation response.

11. The processing system of claim 8 , wherein the memory management circuitry is further to:
receive a command to exit the pause of the communication between the I/O device and the memory.

12. The processing system of claim 11 , wherein the memory management circuitry is further to:
in response to receiving the command to exit the pause of the communication, transmit requested page translations to the I/O device.

13. The processing system of claim 11 , wherein the memory management circuitry is further to:
in response to receiving the command to exit the pause of the communication, transmit a response to a page fault request from the I/O device.

14. The processing system of claim 11 , wherein the memory management circuitry receives the command to exit the pause of the communication from system software.

15. A method comprising;
receiving, by memory management circuitry during execution of instructions by a core, from memory to the memory management circuitry, a command to pause communication between an input/output (I/O) device that supports page faults and the memory, the memory management circuitry being coupled to the memory, the core, and the I/O device, wherein the command to pause communication between the I/O device and the memory is transmitted based on memory consumption or bandwidth congestion;
modifying, by page translation permission circuitry of the memory management circuitry, permissions of page translation responses to generate modified permissions in response to the command to pause the communication; and
transmitting, by express invalidations circuitry of the memory management circuitry to the I/O device, an invalidation request to cause cached page translations in the I/O device to be invalidated in response to the command to pause the communication between the I/O device and the memory.

16. The method of claim 15 , further comprising:
transmitting, by the page translation permission circuitry, a translation response comprising the modified permissions to the I/O device in response to a translation request being received by the memory management circuitry from the I/O device.

17. The method of claim 16 , further comprising:
forgoing transmitting a response to a page fault request from the I/O device, the page fault request being transmitted by the I/O device in response to the translation response.

18. The method of claim 15 , further comprising:
receiving a command to exit the pause of the communication between the I/O device and the memory.

Assignees

• Intel Corp

Inventors

• Vakharwala Rupin
• Firoozshahian Amin
• Van Doren Stephen
• Sankaran Rajesh
• Madhav Mahesh
• Azizi Omid
• Kleen Andreas
• Maddury Mahesh
• Raj Ashok

Classifications

• G06F12/1081 Primary

  for peripheral access to main memory, e.g. direct memory access [DMA] · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F2212/6028

  Prefetching based on hints or prefetch instructions · CPC title

• G06F12/1027

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title