Device with integration of light-emitting diode, light sensor, and bio-electrode sensors on a substrate

US11164992B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11164992-B2
Application numberUS-201916681974-A
CountryUS
Kind codeB2
Filing dateNov 13, 2019
Priority dateJul 31, 2018
Publication dateNov 2, 2021
Grant dateNov 2, 2021

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes at least one electrode disposed on the third portion of the substrate, a first conductor in contact with the multilayer LED stack, and a second conductor in contact with the optical sensor. The at least one electrode, the first conductor, and the second conductor are formed of a glassy carbon material.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of fabricating a semiconductor device comprising: receiving a substrate; forming a buffer layer on the substrate; forming a multilayer light-emitting diode (LED) stack on the buffer layer; etching a portion of the multilayer LED stack to form an optical sensor region trench; forming a dielectric inner spacer on at least one side of the optical sensor region trench; growing an optical sensor epitaxy in the optical sensor region trench to form an optical sensor in contact with the dielectric inner spacer; depositing a contact material on the multilayer LED stack and the dielectric inner spacer; etching portions of the multilayer LED stack to form an optical sensor conductor region, an LED conductor region, and a glassy carbon electrode conductor region; depositing a glassy carbon material in the optical sensor conductor region, the LED conductor region, and the glassy carbon electrode conductor region; and etching the glassy carbon material to form an optical sensor conductor, a multilayer LED stack conductor and glassy carbon electrodes disposed on a portion of the buffer layer. 2. The method of claim 1 , further comprising depositing a dielectric capping layer on the multilayer LED stack. 3. The method of claim 2 , further comprising: applying a first photoresist layer to portions of dielectric capping layer; patterning the optical sensor using a lithographic patterning process; and removing the first photoresist layer. 4. The method of claim 1 , wherein forming the dielectric inner spacer on at least one side of the optical sensor region trench further includes: depositing an optical sensor dielectric layer on the optical sensor region trench; and etching away portions of the optical sensor dielectric layer to form the dielectric inner spacer. 5. The method of claim 1 , further comprising: applying a second photoresist layer to the contact material; patterning the optical sensor conductor region, the LED conductor region, and the glassy carbon electrode conductor region; and removing the second photoresist layer. 6. The method of claim 1 , further comprising: applying a third photoresist layer to the optical sensor region and the multilayer LED stack region; patterning portions of the buffer layer; and removing the third photoresist layer. 7. The method of claim 1 , further comprising: depositing a spacer dielectric on portions of the substrate, the buffer layer, the optical sensor, the multilayer LED stack, and the contact material; and etching the spacer dielectric to form at least one dielectric outer spacer proximate to one or more remaining portions of the buffer layer, portions of the optical sensor, and the multilayer LED stack. 8. The method of claim 1 , further comprising: depositing a hard mask material on the glassy carbon material. 9. The method of claim 8 , wherein the hard mask material is a titanium (Ti) material. 10. The method of claim 8 , further comprising: applying a fourth photoresist layer to portions of the hard mask material; patterning the glassy carbon conductor region; and removing the fourth photoresist layer. 11. The method of claim 1 , wherein the substrate is a sapphire substrate. 12. The method of claim 1 , wherein the buffer layer is formed of a zirconium diboride (ZrB2) material. 13. The method of claim 1 , wherein the multilayer LED stack is a gallium nitride (GaN) multilayer LED stack. 14. The method of claim 1 , wherein the optical sensor is a gallium nitride (GaN) optical sensor.

Assignees

Inventors

Classifications

  • Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

  • Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title

  • characterised by their material · CPC title

  • containing nitrogen, e.g. GaN · CPC title

  • the light-emitting regions comprising nitride materials · CPC title

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Frequently asked questions

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What does patent US11164992B2 cover?
A semiconductor device includes a substrate and a buffer layer disposed on a first portion, a second portion, and a third portion of the substrate. The semiconductor device further includes a multilayer light-emitting diode (LED) stack disposed on the first portion of the substrate, and an optical sensor disposed on the second portion of the substrate. The semiconductor device further includes …
Who is the assignee on this patent?
IBM
What technology area does this patent fall under?
Primary CPC classification H10H20/0137. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 02 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).