Vertical SiC MOSFET

Patent metadata

Field	Value
Publication number	US-11164971-B2
Application number	US-201716086212-A
Country	US
Kind code	B2
Filing date	Jan 30, 2017
Priority date	Mar 31, 2016
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

A vertical SiC MOSFET having a source terminal, a drain terminal, and a gate region, as well as an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type, is furnished, a horizontally extending intermediate layer, which has regions having a doping of a second type different from the doping of a first type, being embedded into the epitaxial layer. The vertical SiC MOSFET is notable for the fact that at least the regions having doping of a second type are electrically conductively connected to the source terminal. The gate region can be disposed in a gate trench.

First claim

What is claimed is:

1. A vertical SiC MOSFET, comprising:
a source terminal;
a drain terminal;
a gate region;
an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type; and
a horizontally extending intermediate layer that is embedded into the epitaxial layer to divide the epitaxial layer into an upper region facing the source terminal and a lower region facing the drain terminal, wherein the intermediate layer includes second-doping-type regions having a doping of a second type different from the doping of the first type, the regions being embedded into the epitaxial layer, wherein at least the regions having doping of the second type are electrically conductively connected to the source terminal, wherein the upper region and the lower region have different doping concentrations, and properties of the MOSFET are adjusted by selecting the doping concentrations of the upper region and the lower region.

2. The vertical SiC MOSFET as recited in claim 1 , wherein the intermediate layer includes first-doping-type regions and the second-doping-type regions.

3. The vertical SiC MOSFET as recited in claim 2 , wherein:
the first-doping-type regions of the intermediate layer are adjoined vertically at least one of in a direction of the source terminal and in a direction of the drain terminal by transition regions having a heavier doping of the first type as compared with the epitaxial layer, and
the epitaxial layer is at least in part adjacent to the second-doping-type regions of the intermediate layer.

4. The vertical SiC MOSFET as recited in claim 2 , wherein the first-doping-type regions of the intermediate layer include one of a double-funnel-shaped profile and an hourglass-shaped profile.

5. The vertical SiC MOSFET as recited in claim 1 , wherein the second-doping-type regions are not completely cleared out when a voltage less than or equal to a blocking voltage of the SiC MOSFET is applied such that quasi-neutral areas are still present in the second-doping-type regions even after application of the blocking voltage.

6. The vertical SiC MOSFET as recited in claim 1 , wherein the intermediate layer is disposed entirely below the gate region such that the intermediate layer is disposed vertically between the gate region and the drain terminal.

7. The vertical SiC MOSFET as recited in claim 1 , wherein the intermediate layer and the epitaxial layer functionally constitute a junction field effect transistor.

8. The vertical SiC MOSFET as recited in claim 7 , wherein a pinch voltage of the junction field effect transistor is in the range between 1 V and 50% of a breakdown voltage of the SiC MOSFET.

9. The vertical SiC MOSFET as recited in claim 7 , wherein a channel of the junction field effect transistor and a channel of the MOSFET are disposed vertically one above another.

10. The vertical SiC MOSFET as recited in claim 7 , wherein the junction field effect transistor is connected electrically in series with the MOSFET.

11. The vertical SiC MOSFET as recited in claim 1 , further comprising:
a transition layer having heavier doping of the first type as compared with the epitaxial layer, the transition layer vertically adjoining the intermediate layer in at least one of a direction of the source terminal and in a direction of the drain terminal.

12. The vertical SiC MOSFET as recited in claim 1 , further comprising:
a transition layer having heavier doping of the first type as compared with the epitaxial layer, the transition layer vertically adjoining the epitaxial layer in a direction of the source terminal.

13. The vertical SiC MOSFET as recited in claim 1 , wherein the upper region, disposed between the source terminal and the intermediate layer, of the epitaxial layer has heavier doping of the first type than the lower region, disposed between the intermediate layer and the drain terminal, of the epitaxial layer.

14. The vertical SiC MOSFET as recited in claim 13 , wherein the heavier doping of the first type that is heavier by a factor of 2 to 4.

15. A control device for a motor vehicle, comprising:
a vertical SiC MOSFET, the MOSFET including:
a source terminal;
a drain terminal;
a gate region;
an epitaxial layer disposed between the source terminal and the drain terminal and having a doping of a first type; and
a horizontally extending intermediate layer that is embedded into the epitaxial layer to divide the epitaxial layer into an upper region facing the source terminal and a lower region facing the drain terminal, wherein the intermediate layer includes second-doping-type regions having a doping of a second type different from the doping of the first type, the regions being embedded into the epitaxial layer, wherein at least the regions having doping of the second type are electrically conductively connected to the source terminal, wherein the upper region and the lower region have different doping concentrations, and properties of the MOSFET are adjusted by selecting the doping concentrations of the upper region and the lower region.

Assignees

• Bosch Gmbh Robert

Inventors

• Jacke Thomas
• Feiler Wolfgang

Classifications

• H10D84/40

  characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs · CPC title

• H10D62/8325

  Silicon carbide · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D30/66

  Vertical DMOS [VDMOS] FETs · CPC title

• H10D30/831

  Vertical FETs having PN junction gate electrodes (Vertical SIT H10D30/202) · CPC title