Ceramic electronic device and manufacturing method of ceramic electronic device

Patent metadata

Field	Value
Publication number	US-11164701-B2
Application number	US-201816208308-A
Country	US
Kind code	B2
Filing date	Dec 3, 2018
Priority date	Dec 8, 2017
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

A ceramic electronic device includes: a multilayer chip including a multilayer structure and cover layers, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic, the cover layers being provided on an upper face and a lower face of the multilayer structure in a stacking direction; and a pair of external electrodes that are formed on the two edge faces, wherein each of the external electrodes has a smaller thickness on a corner portion of the cover layers, has a crook toward the internal electrode layers, and has a larger thickness on an area of the two edge faces where the internal electrode layers are extracted.

First claim

What is claimed is:

1. A ceramic electronic device comprising:
a multilayer chip comprising a multilayer structure and cover layers and having a parallelepiped shape, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic, the cover layers being provided on an upper face and a lower face of the multilayer structure in a stacking direction; and
a pair of external electrodes that are formed on the two edge faces,
wherein each of the external electrodes has a smaller thickness on a corner portion of the cover layers, has a crook toward the internal electrode layers, and has a larger thickness on an entire area of the two edge faces where the internal electrode layers are extracted than on any other areas of the two edge faces,
wherein each of the external electrodes is constituted solely by a conductive portion that is conductive together with the internal electrode layers,
wherein an angle θa is 5° or more and 15° or less, when a straight line parallel with the internal electrode layer next to the cover layer is a first straight line, a straight line that is parallel with the internal electrode next to the cover layer and passes through a half of a thickness of the cover layer is a second straight line, a point where the second straight line crosses a surface of the external electrode is a first point, a straight line passing through the first point and parallel with an interface between an area of the edge face where the internal electrode layers are extracted and the external electrode is a third straight line, a point where the first straight line crosses the surface of the external electrode is a second point, and an angle between a straight line passing through the first point and the second point and the third straight line is the angle θa, in a cross section parallel with a direction passing through a half of a width of the internal electrode layer and parallel with a facing direction of the two edge faces.

2. The ceramic electronic device as claimed in claim 1 , wherein the crook is positioned between an outermost internal electrode layer and a half of a thickness of the cover layer next to the outermost internal electrode layer.

3. The ceramic electronic device as claimed in claim 1 , wherein the thickness of the cover layers is a half of the thickness of the multilayer structure or more.

4. The ceramic electronic device as claimed in claim 1 , wherein a main component of the internal electrode layers and a main component of the external electrodes are the same metal as each other.

5. The ceramic electronic device as claimed in claim 1 , wherein
an entire area of each of the external electrodes facing the area of the two edge faces where the internal electrode layers are extracted has a thickness of 10 μm or more.

6. A manufacturing method of a ceramic electronic device comprising: forming a ceramic multilayer structure having a parallelepiped shape, by stacking a plurality of pattern-formed sheets in each of which a conductive paste for forming internal electrode layers is printed on a part of a dielectric green sheet including ceramic, a margin paste including ceramic is printed on another part of the dielectric green sheet where the conductive paste for forming internal electrode layers is not printed, each of a plurality of conductive pastes for forming internal electrode layers being alternately exposed to two edge faces of the ceramic multiplayer structure, and by providing cover sheets on an upper face and a lower face of the ceramic multilayer structure in a stacking direction of the ceramic multilayer structure; coating a conductive paste for forming external electrodes from the two edge faces to the cover sheets; forming dielectric layers, internal electrode layers, cover layers and external electrodes from the dielectric green sheets, the conductive pastes for forming internal electrode layers, the cover sheets and the conductive pastes for forming external electrodes by firing the ceramic multilayer structure and the conductive paste for forming external electrodes; decreasing a thickness of a part of the external electrode on a corner portion of the cover layer, making a crook of the external electrode toward the internal electrode layers, and increasing a thickness of another part of the external electrode on an area of the two edge faces where the internal electrode layers are extracted, by adjusting a difference between wettability of an area of the two edge faces where the conductive paste for forming internal electrode layers is provided and wettability of a corner portion of the cover sheet, wherein each of the external electrodes has a smaller thickness on the corner portion of the cover layers has the crook toward the internal electrode lavers, and has a larger thickness on an entire area of the two edge faces where the internal electrode layers are extracted than on any other areas of the two edge faces, wherein each of the external electrodes is constituted solely by a conductive portion that is conductive together with the internal electrode layers, wherein an angle θa is 5° or more and 15° or less, when a straight line parallel with the internal electrode layer next to the cover layer is a first straight line, a straight line that is parallel with internal electrode next to the cover layer and passes through a half of a thickness of the cover layer is a second straight line, a point where the second straight line crosses a surface of the external electrode is a first point, a straight line rising throw h the first point and parallel with an interface between an area of the edge face where the internal electrode layers are extracted and the external electrode is a third straight line, a point where the first straight line passing through the first point and the second point and the third straight line is the angle θa, in a cross parallel with a facing direction of the two edge faces.

7. The method as claimed in claim 6 , wherein a difference between the wettability of the area of the two edge faces where the conductive past for forming internal electrode layers are provided and the wettability of the corner portion of the cover sheet is adjusted by enlarging amounts of a binder in the cover sheet and the margin paste more than an amount of a binder in the dielectric green sheets.

8. A ceramic electronic device comprising:
a multilayer chip comprising a multilayer structure, an upper cover layer, and a lower cover layer, the multilayer chip having a parallelepiped shape, the multilayer structure having a structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to two edge faces of the multilayer chip, a main component of the plurality of dielectric layers being a ceramic, the upper cover layer being provided on an upper face of the multilayer structure in a stacking direction; the lower cover layer being provided on a lower face, opposite to the upper face, of the multilayer structure in the stacking direction; and
a pair of external electrodes that are formed on the two edge faces,
wherein each of the external electrodes has a first thickness at each corner portion of an upper face of the upper and an lower face of the lower cover layers and a second thickness on and parallel with each of the upper face of the upper cover layer and the lower face of the lower cover layer, has a crook toward the internal

Assignees

• Taiyo Yuden Kk

Inventors

• Tahara Mikio
• Nakamura Tomoaki

Classifications

• H01G4/248 Primary

  the terminals embracing or surrounding the capacitive element, e.g. caps (H01G4/252 takes precedence) · CPC title

• H01G4/012

  Form of non-self-supporting electrodes · CPC title

• H01G4/232

  electrically connecting two or more layers of a stacked or rolled capacitor · CPC title

• H01G4/0085

  Fried electrodes · CPC title

• H01G4/1227

  based on alkaline earth titanates · CPC title