Semiconductor memory device

Patent metadata

Field	Value
Publication number	US-11164639-B2
Application number	US-201916561094-A
Country	US
Kind code	B2
Filing date	Sep 5, 2019
Priority date	Dec 21, 2018
Publication date	Nov 2, 2021
Grant date	Nov 2, 2021

Abstract

According to one embodiment, a semiconductor memory device includes: a memory cell array; a conversion circuit; a data bus; a first buffer and a second buffer; and a third buffer. The data bus includes a first wiring part extending along a first direction. The first buffer and the second buffer are separate from each other. The first to third buffers are at different positions along the first direction.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a memory cell array comprising a plurality of memory cells;
a conversion circuit configured to convert parallel data into serial data, and serial data into parallel data;
a data bus comprising a first data line, a second data line, and a third data line, the data bus configured to transmit data signals between the memory cell array and the conversion circuit concurrently through the first data line, the second data line, and the third data line;
a first buffer and a second buffer on the first data line;
a third buffer and a fourth buffer on the second data line; and
a fifth buffer and a sixth buffer on the third data line,
wherein the first data line extends along a first direction,
the first buffer, the third buffer, and the fifth buffer are aligned along a second direction different from the first direction,
the second buffer, the fourth buffer, and the sixth buffer are aligned along the second direction,
the first to the third data lines include a first region, a second region, and a third region, the second region being between the first region and the third region,
in the first region, the first to third data lines are parallel with one another,
in the third region, the first to third data lines are parallel with one another in an order different from an order of the first to third data lines in the first region, and
in the second region, at least two of the first to the third data lines cross over one another.

2. The device according to claim 1 , wherein the first to the sixth buffers are each configured to receive a data signal, invert a logic level of the data signal, and output the data signal.

3. The device according to claim 1 , wherein the first buffer, the fourth buffer, and the fifth buffer are each configured to receive a data signal, invert a logic level of the data signal, and output the data signal, and the second buffer, the third buffer, and the sixth buffer are each configured to receive a data signal and output the data signal without inverting a logic level of the data signal.

4. The device according to claim 1 , further comprising:
a seventh buffer on the first data line;
an eighth buffer on the second data line; and
a ninth buffer on the third data line,
wherein the seventh buffer comprises a first transistor configured to output a signal to the first data line,
the eighth buffer comprises a second transistor configured to output a signal to the second data line,
the ninth buffer comprises a third transistor configured to output a signal to the third data line, and
the first transistor differs in size from at least one of the second transistor and the third transistor.

5. The device according to claim 4 , wherein the memory cell array comprises a first memory cell array for a first plane, and a second memory cell array for a second plane,
the seventh buffer is configured to output a data signal from the first memory cell array to the first data line,
the eighth buffer is configured to output a data signal from the first memory cell array to the second data line,
the ninth buffer is configured to output a data signal from the first memory cell array to the third data line,
the device further comprises a tenth buffer configured to output a data signal from the second memory cell array to the first data line, an eleventh buffer configured to output a data signal from the second memory cell array to the second data line, and a twelfth buffer configured to output a data signal from the second memory cell array to the third data line,
the first data line from the tenth buffer to the conversion circuit is longer than the first data line from the seventh buffer to the conversion circuit,
the second data line from the eleventh buffer to the conversion circuit is longer than the second data line from the eighth buffer to the conversion circuit, and
the third data line from the twelfth buffer to the conversion circuit is longer than the third data line from the ninth buffer to the conversion circuit.

6. The device according to claim 5 , wherein the tenth buffer comprises a fourth transistor configured to output a signal to the first data line,
the eleventh buffer comprises a fifth transistor configured to output a signal to the second data line,
the twelfth buffer comprises a sixth transistor configured to output a signal to the third data line, and
the fourth transistor differs in size from at least one of the fifth transistor and the sixth transistor.

7. The device according to claim 4 , wherein the first buffer and the second buffer each comprise a fourth transistor configured to output a signal to the first data line,
the third buffer and the fourth buffer each comprise a fifth transistor configured to output a signal to the second data line,
the fifth buffer and the sixth buffer each comprise a sixth transistor configured to output a signal to the third data line, and
the fourth transistor of the first buffer differs in size from at least one of the fourth transistor of the second buffer, the fifth transistor, and the sixth transistor.

8. The device according to claim 1 , wherein the first direction is orthogonal to the second direction.

9. The device according to claim 4 , wherein the first buffer and the second buffer each comprise a fourth transistor configured to output a signal to the first data line,
the third buffer and the fourth buffer each comprise a fifth transistor configured to output a signal to the second data line,
the fifth buffer and the sixth buffer each comprise a sixth transistor configured to output a signal to the third data line, and
the fourth transistor of the second buffer differs in size from at least one of the fourth transistor of the first buffer, the fifth transistor, and the sixth transistor.

Assignees

• Toshiba Memory Corp

Inventors

• Noro Hiromi
• Ochi Yusuke
• Sugimoto Takahiro
• Kanagawa Naoaki

Classifications

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C16/0483 Primary

  comprising cells having several storage transistors connected in series · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title