Residue checking of entire normalizer output of an extended result

Patent metadata

Field	Value
Publication number	US-11159183-B2
Application number	US-201916453395-A
Country	US
Kind code	B2
Filing date	Jun 26, 2019
Priority date	Jun 26, 2019
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A method includes generating an extended result from a first operation circuitry having a result register bit width greater than a bus width associated with a residue check path of a second operation circuitry associated with a floating point unit. An extended result residue less a first portion residue of the extended result received from the residue check path is stored as a first partial result residue. The first partial result residue is compared with a first result residue of the second operation circuitry. The extended result residue less both the first partial result residue and a second portion residue of the extended result received from the residue check path as a second partial result residue is compared with a second result residue of the second operation circuitry.

First claim

What is claimed is:

1. A method comprising:
receiving, at a normalizer, an extended result from first operation circuitry of a floating point unit, wherein the extended result comprises a first set of bits comprising leading zeros of the extended result, a second set of bits, a third set of bits, and a fourth set of bits comprising remaining bits to the right of the third set of bits;
determining a residue of the extended result;
determining a first normalizer result during a first normalizer cycle, the first normalizer result comprising the second set of bits;
determining a first portion residue of the extended result, the first portion residue comprising a loss to the right of the normalizer during the first normalizer cycle, wherein the loss to the right of the normalizer during the first normalizer cycle comprises the third set of bits and the fourth set of bits;
storing the residue of the extended result less the first portion residue of the extended result as a first partial result residue;
determine a first result residue of the second set of bits;
comparing the first partial result residue with the first result residue;
determining a second normalizer result during a second normalizer cycle, the second normalizer result comprising the third set of bits;
determining a second portion residue of the extended result, the second portion residue comprising a loss to the right of the normalizer during the second normalizer cycle, wherein the loss to the right of the normalizer during the second normalizer cycle comprises the fourth set of bits;
storing the residue of the extended result less the second portion residue and the first partial result residue as a second partial result residue;
determine a second result residue of the third set of bits;
comparing the second partial result residue with the second result residue; and
operating the floating point unit according to the comparison of the first partial result residue with the first result residue and the comparison of the second partial result residue with the second result residue.

2. The method of claim 1 , wherein the first operation circuitry is an adder or a multiplier.

3. The method of claim 1 , wherein the operation of the floating point unit includes outputting an error responsive to one or both of the comparison of the first partial result residue with the first result residue and the comparison of the second partial result residue with the second result residue such that operation of the floating point unit is stopped.

4. The method of claim 3 , wherein the operation of the floating point unit includes outputting the error such that operation of the floating point unit is restarted.

5. The method of claim 1 , wherein the extended result includes an extended result bit width that is equal to a first input operand bit width and a second input operand bit width combined.

6. A system comprising:
a floating point unit including first operation circuitry operable to store an extended result and a normalizer operable to receive the extended result, wherein the extended result comprises a first set of bits comprising leading zeros of the extended result, a second set of bits, a third set of bits, and a fourth set of bits comprising remaining bits to the right of the third set of bits; and
residue check circuitry associated with the floating point unit that includes a residue check latch;
wherein the floating point unit is configured to:
determine a residue of the extended result;
determine a first normalizer result during a first normalizer cycle, the first normalizer result comprising the second set of bits;
determine a first portion residue of the extended result, the first portion residue comprising a loss to the right of the normalizer during the first normalizer cycle, wherein the loss to the right of the normalizer during the first normalizer cycle comprises the third set of bits and the fourth set of bits;
store the residue of the extended result less the first portion residue of the extended result as a first partial result residue;
determine a first result residue of the second set of bits;
compare the first partial result residue with the first result residue;
determine a second normalizer result during a second normalizer cycle, the second normalizer result comprising the third set of bits;
determine a second portion residue of the extended result, the second portion residue comprising a loss to the right of the normalizer during the second normalizer cycle, wherein the loss to the right of the normalizer during the second normalizer cycle comprises the fourth set of bits;
store the residue of the extended result less the second portion residue and the first partial result residue as a second partial result residue;
determine a second result residue of the third set of bits; and
compare the second partial result residue with the second result residue.

7. The system of claim 6 , wherein the residue check circuitry is operable to:
compare an extended result residue associated with the extended result less a first portion residue of the extended result with the first result residue; and
compare the extended result residue less the first partial result residue as a second partial result residue with a second result residue of the normalizer.

8. The system of claim 7 , wherein the floating point unit is operable to stop operation of the first operation circuitry and the normalizer based on results of the comparisons of:
the first partial result residue with the first result residue of the normalizer; and
the second partial result residue with the second result residue of the normalizer.

9. The system of claim 6 , wherein the extended result is equal to or less than a first input operand bit width and a second input operand bit width combined.

Assignees

• IBM

Inventors

• Hofmann Nicol
• Klein Michael
• Schelm Kerstin Claudia
• Figuli Razvan Peter

Classifications

• H03M13/096

  Checksums · CPC title

• G06F7/72 Primary

  using residue arithmetic · CPC title

• G06F7/483

  Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers {(G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence)} · CPC title

• G06F7/24

  Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers {sorting methods in general}(G06F7/36 takes precedence) · CPC title

• H03M13/6586 Primary

  Modulo/modular normalization, e.g. 2's complement modulo implementations · CPC title