Background calibration of non-linearity of samplers and amplifiers in ADCs

Patent metadata

Field	Value
Publication number	US-11159169-B2
Application number	US-202016877118-A
Country	US
Kind code	B2
Filing date	May 18, 2020
Priority date	Feb 2, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

Analog circuits are often non-linear, and the non-linearities can hurt performance. Designers would trade off power consumption to achieve better linearity. An efficient and effective calibration technique can address the non-linearities and reduce the overall power consumption. A dither signal injected to the analog circuit can be used to expose the non-linear behavior in the digital domain. To detect the non-linearities, a counting approach is applied to isolate non-linearities independent of the input distribution. The approach is superior to and different from other approaches in many ways.

First claim

What is claimed is:

1. A method for efficient error estimation and calibration of a circuit, comprising:
adding a dither at an input of the circuit;
removing the dither at an output of the circuit;
determining a sign bit of the dither;
determining whether a given sample of the output is within a first range on the output defined by a first inspection point;
determining whether the given sample of the output is within a second range on the output defined by a second inspection point;
determining a first partial error by logically combining the sign bit of the dither and whether the given sample of the output is within the first range;
determining a second partial error by logically combining the sign bit of the dither and whether the given sample of the output is within the second range;
updating an estimate of a component of a circuit on a sample-by-sample basis based on the first partial error and the second partial error; and
calibrating the circuit based on the estimate of the component of the circuit.

2. The method of claim 1 , wherein:
determining the first partial error comprises setting the first partial error to be the sign bit of the dither, if a given sample is within a first range on the output defined by a first inspection point; and
determining the second partial error comprises setting the second partial error to be the sign bit of the dither, if the given sample is within a second range on the output defined by a second inspection point.

3. The method of claim 1 , wherein:
determining the first partial error comprises setting the first partial error to be zero, if the given sample is not within a first range defined by a first inspection point; and
determining the second partial error comprises setting the second partial error to be zero, if the given sample is not within a second range defined by a second inspection point.

4. The method of claim 1 , wherein updating the estimate of the component of the circuit further comprises:
determining an error estimate based on the first and second partial errors; and
updating the estimate of a component of the circuit based on the error estimate.

5. The method of claim 2 , wherein:
the first inspection point is a positive inspection point; and
the second inspection point is a negative inspection point.

6. The method of claim 2 , wherein:
the first inspection point and the second inspection point are the same; and
the first range does not overlap with the second range.

7. The method of claim 1 , wherein updating the estimate of the component of the circuit comprises:
setting an error estimate based on a sign bit of the dither and a sign bit of the output; and
updating the estimate of a component of the circuit based on the error estimate.

8. A calibration system with efficient error estimation, comprising:
dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
a first operation to determine whether a corrected output of the circuit is within a first range defined by a first inspection point;
a second operation to obtain a sign of the dither;
a third operation to obtain a first partial error at the first inspection point by logically combining outputs of the first operation and the second operation; and
calibration circuitry to update an estimate of a component of the circuit based on the first partial error at the first inspection point and a second partial error, wherein the second partial error is based on a second inspection point and the sign of the dither.

9. The calibration system of claim 8 , wherein the second operation obtains a sign bit of the dither.

10. The calibration system of claim 8 , further comprising:
a fourth operation to determine whether the corrected output of the circuit is within a second range defined by the second inspection point;
a fifth operation to obtain the sign of the dither; and
a sixth operation to obtain the second partial error at the first inspection point by logically combining outputs of the fourth operation and the fifth operation.

11. The calibration system of claim 10 , wherein the fifth operation obtains a sign bit of the dither.

12. The calibration system of claim 10 , further comprising:
error circuitry to combine an output of the third operation and an output of the sixth operation and form an error estimate; and
wherein the calibration circuitry drives the error estimate towards zero.

13. The calibration system of claim 10 , wherein:
the first inspection point is a positive inspection point; and
the second inspection point is a negative inspection point.

14. The calibration system of claim 10 , wherein:
the first inspection point and the second inspection point are the same; and
the first range does not overlap with the second range.

15. The calibration system of claim 10 , wherein:
the first inspection point and the second inspection point are zero; and
the first range does not overlap with the second range.

16. A calibration system with efficient error estimation, comprising:
dither circuitry to inject a dither at an input of a circuit and to remove the dither at an output of the circuit;
error circuitry to:
compute a first partial error by logically combining a sign bit of the dither and whether a given sample of the output is within a first range on the output defined by a first inspection point;
compute a second partial error by logically combining a sign bit of the dither and whether the given sample of the output is within a second range on the output defined by a second inspection point; and

calibration circuitry to update an estimate of a component of the circuit based on the first and second partial errors computed for successive samples of the output of the circuit.

17. The calibration system of claim 16 , wherein the error circuitry is to:
set the first partial error to be a sign bit of the dither, if the given sample is within the first range on the output defined by the first inspection point; and
set the second partial error to be a sign bit of the dither, if the given sample is within the second range on the output defined by the second inspection point.

18. The calibration system of claim 16 , wherein the error circuitry is to:
set the first partial error to be zero, if the given sample is not within the first range defined by the first inspection point; and
set the second partial error to be zero, if the given sample is not within the second range defined by the second inspection point.

19. The calibration system of claim 16 , wherein the error circuitry comprises:
a sign operation to determine the sign bit of the dither;
a hit operation to determine whether the given sample is within the first range or the second range; and
an AND operation to logically combine outputs of the sign operation and the hit operation.

20. The calibration system of claim 16 , wherein the error circuitry comprises:
a first sign operation to determine a sign bit of the dither;
a second sign operation to determine a sign bit of the given sample; and

an AND operation to logically combine outputs of the first sign operation and the second sign operation.

Assignees

• Analog Devices Inc

Inventors

• Ali Ahmed Mohamed Abdelatty
• Gulati Paridhi

Classifications

• H03M1/0641 Primary

  the dither being a random signal · CPC title

• H03M1/1009

  Calibration · CPC title

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M3/348

  using return-to-zero signals · CPC title

• H03M3/358

  of non-linear distortion, e.g. instability (avoiding instability by structural design H03M3/44) · CPC title