Power amplifier time-delay invariant predistortion methods and apparatus

Patent metadata

Field	Value
Publication number	US-11159129-B2
Application number	US-202016901116-A
Country	US
Kind code	B2
Filing date	Jun 15, 2020
Priority date	May 1, 2002
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

An embodiment of the invention is a time-delay invariant predistortion approach to linearize power amplifiers in wireless RF transmitters. The predistortion architecture is based on the stored-compensation or memory-compensation principle by using a combined time-delay addressing method, and therefore, the architecture has an intrinsic, self-calibrating time-delay compensation function. The predistortion architecture only uses a lookup table to conduct both the correction of non-linear responses of a power amplifier and the compensation of any time-delay effects presented in the same system. Due to the time-delay invariant characteristic, the predistortion design has a wider dynamic range processing advantage for wireless RF signals, and therefore can be implemented in multi-carrier and multi-channel wireless systems.

First claim

What is claimed is:

1. A predistortion system for linearizing an output of a power amplifier, the predistortion system comprising;
a first receiver that receives a first signal representative of a radio frequency (RF) modulated signal;
a second receiver that receives a feedback signal representative of at least one nonlinear characteristic of a power amplifiers;
a predistortion controller that is communicatively coupled to the first receiver via a reference path, is communicatively coupled to the second receiver via a feedback path, and generates, based on at least one time-delay correction element, a correction factor to correct the at least one nonlinear characteristic of the power amplifier,
wherein the predistortion controller includes at least one lookup table that is pre-populated with the at least one time-delay correction element that compensates for a time delay between the reference path and the feedback path.

2. The predistortion system of claim 1 , wherein:
the time-delay correction element is associated with a set of inputs, and
the set of inputs includes a first difference between:
a square of a quadrature component of the first signal, and
a square of a quadrature component of the feedback signal.

3. The predistortion system of claim 2 , wherein the set of inputs includes a second difference between:
a square of an in-phase component of the first signal, and
a square of an in-phase component of the feedback signal.

4. The predistortion system of claim 1 , wherein the predistortion controller adaptively updates at least one correction value included in the at least one lookup table by combining a non-linear correction value of the power amplifier with the time-delay correction element.

5. The predistortion system of claim 1 , further comprising a processor that combines the RF modulated signal with a second signal corresponding to the correction factor to generate a combined RF modulated signal.

6. The predistortion system of claim 5 , wherein the processor supplies the combined RF modulated signal with the feedback signal to the power amplifier to linearize the output of the power amplifier.

7. The predistortion system of claim 1 , further comprising combining logic that combines the RF modulated signal with a second signal corresponding to the correction factor to generate a combined RF modulated signal.

8. The predistortion system of claim 7 , wherein the combining logic supplies the combined RF modulated signal and the feedback signal to the power amplifier to linearize the output of the power amplifier.

9. The predistortion system of claim 7 , wherein the second signal is an analog signal.

10. The predistortion system of claim 1 , further comprising a serial shift register that forms addresses for the at least one lookup table.

11. The predistortion system of claim 1 , wherein the at least one lookup table is addressed by parallel signals.

12. The predistortion system of claim 1 , wherein the feedback signal is an analog signal.

13. The predistortion system of claim 12 , further comprising a digital-to-analog (D/A) converter.

14. The predistortion system of claim 13 , wherein the D/A converter is configured to convert a digital signal corresponding to the correction factor included a second signal.

15. The predistortion system of claim 1 , wherein the at least one time-delay correction element falls within a range determined by a predetermined size of the at least one lookup table.

16. The predistortion system of claim 1 wherein the at least one lookup table is configured to respond to inputs derived from outputs of the at least one lookup table.

Assignees

• Dali Wireless Inc

Inventors

• Yang Dali
• Yang Jia

Classifications

• H04L1/0044

  specially adapted for power saving · CPC title

• H04B1/0475

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H03F2200/57

  Separate feedback of real and complex signals being present · CPC title

• H03F1/3241

  using predistortion circuits (H03F1/3211, H03F1/3217 take precedence) · CPC title

• H04B2001/0425

  with linearisation using predistortion · CPC title