Display panel and driving method for driving the display panel

Patent metadata

Field	Value
Publication number	US-11158281-B2
Application number	US-201816633388-A
Country	US
Kind code	B2
Filing date	Nov 26, 2018
Priority date	Nov 26, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

Provided are a display panel and a driving method thereof. The display panel includes an array substrate, the display panel including a display region and a peripheral region. In the peripheral region, a common voltage wiring, a voltage feedback wiring, a periodic signal wiring, and a decoupling wiring are disposed on the array substrate at intervals; the common voltage wiring is configured to transmit a common voltage signal for display to a pixel array in the display region, the voltage feedback wiring is configured to transmit a voltage feedback signal for monitoring changes in the common voltage signal, the periodic signal wiring is configured to provide the pixel array with a periodic signal for display, the decoupling wiring is located between the periodic signal wiring and the voltage feedback wiring, and is configured to transmit a decoupling signal for reducing coupling distortion of the voltage feedback signal.

First claim

What is claimed is:

1. A display panel comprising an array substrate, the display panel comprising a display region and a peripheral region surrounding the display region, wherein:
in the peripheral region, a common voltage wiring, a voltage feedback wiring, a periodic signal wiring, and a decoupling wiring are disposed on the array substrate at intervals;
the common voltage wiring is configured to transmit a common voltage signal for display to a pixel array in the display region,
the voltage feedback wiring is configured to transmit a voltage feedback signal for monitoring changes in the common voltage signal,
the periodic signal wiring is configured to provide the pixel array with a periodic signal for display,
the decoupling wiring is located between the periodic signal wiring and the voltage feedback wiring, and is configured to transmit a decoupling signal for reducing coupling distortion of the voltage feedback signal caused by coupling effect of the periodic signal.

2. The display panel according to claim 1 , wherein the decoupling signal is a periodic pulse signal;
a pulse period of the decoupling signal is equal to a period in which the voltage feedback signal undergoes the coupling distortion,
a phase of the decoupling signal is opposite to a phase of the voltage feedback signal undergoing coupling distortion.

3. The display panel according to claim 2 , wherein a pulse width of the decoupling signal is equal to a time during which the voltage feedback signal undergoes the coupling distortion.

4. The display panel according to claim 2 , wherein a pulse width of the decoupling signal is greater than a time during which the voltage feedback signal undergoes the coupling distortion.

5. The display panel according to claim 1 , wherein the periodic signal wiring includes a clock signal wiring and/or a frame start signal wiring.

6. The display panel according to claim 1 , wherein the display panel further comprises a signal processing circuit,
the signal processing circuit is connected to the decoupling wiring and is configured to output the decoupling signal to the decoupling wiring.

7. The display panel according to claim 1 , wherein in the peripheral region, a ground wiring separated from the voltage feedback wiring is further provided on the array substrate, and an earth capacitance is formed between the voltage feedback wiring and the ground wiring.

8. The display panel according to claim 7 , wherein in the peripheral region, the array substrate further comprises a first conductive layer and a connection electrode,
the first conductive layer is insulated from the ground wiring, an orthographic projection of the first conductive layer on the array substrate and an orthographic projection of the ground wiring on the array substrate at least partially overlap, and the first conductive layer is electrically connected to the voltage feedback wiring, so that the earth capacitance is formed between the first conductive layer and the ground wiring;
the connection electrode is electrically connected to the first conductive layer via a first through hole and is insulated from the ground wiring, and the connection electrode is electrically connected to the voltage feedback wiring via a second through hole.

9. The display panel according to claim 7 , wherein in the peripheral region, the array substrate further comprises a first conductive layer and a connection electrode,
the first conductive layer is insulated from the voltage feedback wiring, an orthographic projection of the first conductive layer on the array substrate and an orthographic projection of the voltage feedback wiring on the array substrate at least partially overlap, and the first conductive layer is electrically connected to the ground wiring, so that the earth capacitance is formed between the first conductive layer and the voltage feedback wiring;
the connection electrode is electrically connected to the first conductive layer via a first through hole and is insulated from the voltage feedback wiring, and the connection electrode is electrically connected to the ground wiring via a second through hole.

10. The display panel according to claim 8 , wherein the first conductive layer and a gate or a source-drain of a thin film transistor in the display region are formed in a same layer and a same material.

11. The display panel according to claim 7 , wherein the ground wiring and the voltage feedback wiring are formed in a same layer and a same material on the array substrate.

12. The display panel according to claim 1 , further comprising an opposite substrate, wherein:
a black matrix is disposed on the opposite substrate, and a thickness of the black matrix disposed in a first region is smaller than a thickness of the black matrix disposed in a second region,
the first region is a region including orthographic projections of the voltage feedback wiring and the periodic signal wiring on the opposite substrate, and the second region is a region on the opposite substrate outside the first region.

13. The display panel according to claim 12 , wherein the first region further comprises a region of orthographic projections of the common voltage wiring and the decoupling wiring on the opposite substrate.

14. The display panel according to claim 12 , wherein the opposite substrate comprises a color film substrate.

15. A driving method for the driving a display panel, said display panel comprising an array substrate, a display region and a peripheral region surrounding the display region, in the peripheral region, a common voltage wiring, a voltage feedback wiring, a periodic signal wiring, and a decoupling wiring are disposed on the array substrate at intervals, the common voltage wiring is configured to transmit a common voltage signal for display to a pixel array in the display region, the voltage feedback wiring is configured to transmit a voltage feedback signal for monitoring changes in the common voltage signal, the periodic signal wiring is configured to provide the pixel array with a periodic signal for display, and the decoupling wiring is located between the periodic signal wiring and the voltage feedback wiring, wherein said driving method comprising:
transmitting the decoupling signal via the decoupling wiring, and the decoupling signal is used to reduce coupling distortion of the voltage feedback signal caused by coupling effect of the periodic signal.

16. The driving method according to claim 15 , wherein the decoupling signal is a periodic pulse signal;
a pulse period of the decoupling signal is equal to a period in which the voltage feedback signal undergoes the coupling distortion,
a phase of the decoupling signal is opposite to a phase of the voltage feedback signal undergoing the coupling distortion.

17. The driving method according to claim 16 , wherein a pulse width of the decoupling signal is equal to a time during which the voltage feedback signal undergoes the coupling distortion.

18. The driving method according to claim 16 , wherein a pulse width of the decoupling signal is greater than a time during which the voltage feedback signal undergoes the coupling distortion.

Assignees

• Fuzhou Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Lv Yaochao
• Cheng Hao
• Li Zongxiang
• Liao Jiamin
• Tao Wenchang
• Hong Guichun
• Wu Zhendian
• Lin Linlin
• Liu Zuwen
• Wang Jin
• Qiu Xinmao
• Shi Changhong
• Zhuang Zihua
• Zhou Min
• Huang Yawen
• Liu Yao
• Zhu Jingguang
• Lin Jiantao
• Chen Xi

Classifications

• G09G2330/06

  Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation · CPC title

• G09G2320/0219

  Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling · CPC title

• G09G2300/043

  Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver · CPC title

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G3/3655

  Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors · CPC title