Pixel circuit suitable for borderless design and display panel including the same

Patent metadata

Field	Value
Publication number	US-11158244-B2
Application number	US-202016880203-A
Country	US
Kind code	B2
Filing date	May 21, 2020
Priority date	Sep 25, 2019
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A pixel circuit including a writing circuit, a compensation circuit, a reset circuit, a brightness control circuit, and a light emission control circuit is provided. The writing circuit provides a first data signal and a second data signal. A first compensation unit of the compensation circuit provides, in a first time period, a first driving current according to the first data signal. A second compensation unit of the compensation circuit provides, in a second time period separated from the first time period, a second driving current according to the second data signal. The reset circuit provides a reference voltage to the compensation circuit. The light emission control circuit conducts the first compensation unit to the brightness control circuit in the first time period, and conducts the second compensation unit to the brightness control circuit in the second time period.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a writing circuit, configured to provide a first data signal and a second data signal;
a compensation circuit, comprising a first compensation circuit and a second compensation circuit, wherein the first compensation circuit is configured to provide, in a first time period, a first driving current according to the first data signal, the second compensation circuit is configured to provide, in a second time period, a second driving current according to the second data signal, and the first time period is separated from the second time period, wherein the first compensation circuit comprises:
a first driving transistor, comprising a first terminal, a second terminal, and a control terminal;
a first compensation switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first compensation switch is coupled with the control terminal of the first driving transistor, the second terminal of the first compensation switch is coupled with the second terminal of the first driving transistor, and the control terminal of the first compensation switch is configured to receive a first scan signal; and
a first capacitor, coupled between the writing circuit and the control terminal of the first driving transistor, and configured to receive the first data signal, wherein the second compensation circuit comprises:
a second driving transistor, comprising a first terminal, a second terminal, and a control terminal;
a second compensation switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second compensation switch is coupled with the control terminal of the second driving transistor, the second terminal of the second compensation switch is coupled with the second terminal of the second driving transistor, and the control terminal of the second compensation switch is configured to receive a second scan signal; and
a second capacitor, coupled between the writing circuit and the control terminal of the second driving transistor, and configured to receive the second data signal,
wherein the first terminal of the first driving transistor and the first terminal of the second driving transistor are coupled, in a parallel connection, with a first power terminal;

a reset circuit, configured to provide a reference voltage to the compensation circuit;
a brightness control circuit; and
a light emission control circuit, coupled with the first compensation circuit, the second compensation circuit, and the brightness control circuit, wherein the light emission control circuit conducts, in the first time period, the first compensation circuit to the brightness control circuit so that the brightness control circuit emits according to the first driving current, and
the light emission control circuit conducts, in the second time period, the second compensation circuit to the brightness control circuit so that the brightness control circuit emits according to the second driving current.

2. The pixel circuit of claim 1 , wherein the light emission control circuit comprises:
a first emission switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first emission switch is coupled with the first compensation circuit, and the control terminal of the first emission switch is configured to receive a first emission signal; and
a second emission switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second emission switch is coupled with the second compensation circuit, and the control terminal of the second emission switch is configured to receive a second emission signal,
wherein the second terminal of the first emission switch and the second terminal of the second emission switch are coupled, in a parallel connection, with the brightness control circuit.

3. The pixel circuit of claim 1 , wherein the reset circuit comprises:
a first reset switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first reset switch is coupled with the first compensation circuit, and the control terminal of the first reset switch is configured to receive a first reset signal; and
a second reset switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the second reset switch is coupled with the second compensation circuit, and the control terminal of the second reset switch is configured to receive a second reset signal,
wherein the second terminal of the first reset switch and the second terminal of the second reset switch are configured to receive the reference voltage.

4. The pixel circuit of claim 1 , wherein the writing circuit comprises:
a first node, configured to provide the first data signal;
a first writing switch, comprising a first terminal, a second terminal, and a control terminal;
a second writing switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the first writing switch and the first terminal of the second writing switch are coupled with the first node;
a second node, configured to provide the second data signal;
a third writing switch, comprising a first terminal, a second terminal, and a control terminal; and
a fourth writing switch, comprising a first terminal, a second terminal, and a control terminal, wherein the first terminal of the third writing switch and the first terminal of the fourth writing switch are coupled with the second node,
wherein the second terminal of the first writing switch and the second terminal of the third writing switch are coupled with a data line, and the second terminal of the second writing switch and the second terminal of the fourth writing switch are configured to receive the reference voltage,
the control terminal of the first writing switch and the control terminal of the fourth writing switch are configured to receive a first emission signal, and the control terminal of the second writing switch and the control terminal of the third writing switch are configured to receive a second emission signal.

5. The pixel circuit of claim 4 , wherein the first emission signal is opposite to the second emission signal.

6. The pixel circuit of claim 4 , wherein the writing circuit is configured to receive a plurality of data voltages from the data line, when the writing circuit outputs the reference voltage as the first data signal, the writing circuit outputs the plurality of data voltages as the second data signal and the second compensation circuit determines magnitude of the second driving current according to a corresponding one of the plurality of data voltages.

7. The pixel circuit of claim 1 , wherein the brightness control circuit comprises:
an input terminal, coupled with the light emission control circuit, and configured to receive the first driving current or the second driving current;
a first light emission element; and
a second light emission element, wherein a first terminal of the first light emission element and a first terminal of the second light emission element are coupled, in a parallel connection, with the input terminal.

8. The pixel circuit of claim 7 , wherein the brightness control circuit further comprises a resistor element, the resistor element is coupled between a second terminal of the second light emission element and a second power terminal, and a second terminal of the first light emission element is coupled with the second power terminal.

9. The pixel circuit of claim 7 , wherein the brightness control circuit further comprises:
a bypass switch,

Assignees

• Au Optronics Corp

Inventors

• Hung Chia-Che
• Cheng Mao-Hsun

Classifications

• G09G3/32 Primary

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G3/2018

  by time modulation using two or more time intervals · CPC title

• G09G3/3208 Primary

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G2300/0439

  Pixel structures · CPC title