System and method for determining hybrid-manufacturing process plans for integrated circuits based on satisfiability modulo difference logic solver

US11157672B1 · US · B1

Patent metadata
FieldValue
Publication numberUS-11157672-B1
Application numberUS-202017023747-A
CountryUS
Kind codeB1
Filing dateSep 17, 2020
Priority dateSep 17, 2020
Publication dateOct 26, 2021
Grant dateOct 26, 2021

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  5. First independent claim

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Abstract

Official abstract text for this publication.

One embodiment of the present disclosure provides a system for determining a hybrid-manufacturing plan for manufacturing an integrated circuit (IC). During operation, the system can obtain a set of hybrid-manufacturing constraints for manufacturing the IC. The set of hybrid-manufacturing constraints can include a set of primitives, a set of atoms, and an atom end-state vector. An atom can correspond to a unit of spatial volume of the IC. A primitive can represent an additive, subtractive, or a mixed manufacturing process corresponding to one or more atoms of the IC. Next, the system can determine a plurality of feasible hybrid-manufacturing plans based on the set of manufacturing constraints. Each feasible hybrid-manufacturing plan can represent an ordering of the set of primitives that satisfies the atom end-state vector. The system can then determine costs for manufacturing the IC using the plurality feasible hybrid-manufacturing plans. The system can determine, based on the costs, an optimized hybrid-manufacturing plan for manufacturing the IC.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for determining a hybrid-manufacturing plan for an integrated circuit (IC), the method comprising: obtaining, by a computer, a set of hybrid-manufacturing constraints for manufacturing the IC, wherein the set of hybrid-manufacturing constraints include a set of primitives, a set of atoms, and an atom end-state vector, wherein an atom corresponds to a unit of spatial volume of the IC, and wherein a primitive represents an additive, subtractive, or a mixed manufacturing process corresponding to one or more atoms of the IC; determining a plurality of feasible hybrid-manufacturing plans based on the set of hybrid-manufacturing constraints, wherein each feasible hybrid-manufacturing plan represents an ordering of the set of primitives that satisfies the atom end-state vector; determining costs for manufacturing the IC using the plurality of feasible hybrid-manufacturing plans; and determining, based on the costs, an optimized hybrid-manufacturing plan for manufacturing the IC. 2. The method of claim 1 , wherein the set of hybrid manufacturing constraints further comprises: a constraint matrix with the columns corresponding to the set of primitives and the rows corresponding to the set of atoms; and an atom cost vector. 3. The method of claim 1 , further comprising converting the set of hybrid-manufacturing constraints to a satisfiability modulo theory (SMT) problem; wherein determining the feasible hybrid-manufacturing plans comprises solving the SMT problem using a Satisfiability (SAT) modulo difference logic. 4. The method of claim 1 , wherein each cost is associated with one or more of: tool set-up cost; shut-down cost; and material cost. 5. The method of claim 1 , wherein the primitive is further categorized into: a preparatory manufacturing process; and a post-processing manufacturing process; and wherein each manufacturing process includes one or more of: a lithography exposure process; a chemical bath process; and a plasma etching process. 6. The method of claim 1 , further comprising converting the set of hybrid-manufacturing constraints to an SMT problem by: generating a conjunctive normal form (CNF) modulo difference logic formula; and converting the CNF difference logic formula to a Boolean formula, wherein the Boolean formula is implemented by using at least one or more Boolean subtractor circuits. 7. The method of claim 6 , wherein determining the plurality of feasible hybrid-manufacturing plans further comprises: for a respective feasible hybrid-manufacturing plan: sorting one or more columns in a constraint matrix based on one or more variables in the feasible hybrid-manufacturing plan, wherein each column corresponds to a primitive, and wherein sorting the one or more columns in the constraint matrix corresponds to changing an order of the set of primitives; determining, for each primitive, an atom count representing a number of atoms added, deleted, or modified; determining an atom cost associated with each primitive; and determining a cost of the feasible hybrid-manufacturing plan by multiplying the atom cost and the atom count for respective primitives and aggregating across the set of primitives. 8. The method of claim 1 , wherein determining the optimized hybrid-manufacturing plan further comprises: applying a binary search to the costs to determine the optimized hybrid-manufacturing plan. 9. A non-transitory computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for determining a hybrid-manufacturing plan for manufacturing an integrated circuit (IC), the method comprising: obtaining a set of hybrid-manufacturing constraints for manufacturing the IC, wherein the set of hybrid-manufacturing constraints include a set of primitives, a set of atoms, and an atom end-state vector, wherein an atom corresponds to a unit of spatial volume of the IC, and wherein a primitive represents an additive, a subtractive, or a mixed manufacturing process corresponding to one or more atoms of the IC; determining a plurality of feasible hybrid-manufacturing plans based on the set of hybrid-manufacturing constraints, wherein each feasible hybrid-manufacturing plan represents an ordering of the set of primitives that satisfies the atom end-state vector; determining costs for manufacturing the IC using the plurality of feasible hybrid-manufacturing plans; and determining, based on the costs, an optimized hybrid-manufacturing plan for manufacturing the IC. 10. The non-transitory computer-readable storage medium of claim 9 , wherein the set of hybrid manufacturing constraints further comprises: a constraint matrix with the columns corresponding to the set of primitives and the rows corresponding to the set of atoms; and an atom cost vector. 11. The non-transitory computer-readable storage medium of claim 9 , wherein the primitive is categorized into: a preparatory manufacturing process; and a post-processing manufacturing process; and wherein each manufacturing process includes one or more of: a lithography exposure process; a chemical bath process; and a plasma etching process. 12. The non-transitory computer-readable storage medium of claim 9 , wherein the method further comprises converting the set of hybrid-manufacturing constraints to a satisfiability modulo theory (SMT) problem; and wherein determining the feasible hybrid-manufacturing plans comprises solving the SMT problem using a Satisfiability (SAT) modulo difference logic. 13. The non-transitory computer-readable storage medium of claim 9 , wherein the method further comprises converting the set of hybrid-manufacturing constraints to an SMT problem by: generating a conjunctive normal form (CNF) modulo difference logic formula; and converting the CNF difference logic formula to a Boolean formula, wherein the Boolean formula is implemented by using at least one or more Boolean subtractor circuits. 14. The non-transitory computer-readable storage medium of claim 13 , wherein determining the plurality of feasible hybrid-manufacturing plans further comprises: for a respective feasible hybrid-manufacturing plan: sorting one or more columns in a constraint matrix based on one or more variables in the feasible hybrid-manufacturing plan, wherein each column corresponds to a primitive, and wherein sorting the one or more columns in the constraint matrix corresponds to changing an order of the set of primitives; determining, for each primitive, an atom count representing a number of atoms added, deleted, or modified; determining an atom cost associated with each primitive; and determining a cost of the feasible hybrid-manufacturing plan by multiplying the atom cost and the atom count for respective primitives and aggregating across the set of primitives. 15. The non-transitory computer-readable storage medium of claim 9 , wherein determining the optimized hybrid-manufacturing plan further comprises: applying a binary search to the costs to determine the optimized hybrid-manufacturing plan. 16. A computer system for determining a hybrid-manufacturing plan for manufacturing an integrated circuit, the system comprising: a processor; and a storage device coupled to the processor and storing instructions, which when executed by the processor cause the processor to perform a method, wherein the method comprises: obtaining a set of hybrid-manufacturing constraints for manufacturing the IC, wherein the set of hybrid-manufacturing constraints include a set of primitives, a set of

Assignees

Inventors

Classifications

  • Constraint-based CAD · CPC title

  • Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

  • Manufacturability analysis or optimisation for manufacturability · CPC title

  • Manufacturing semiconductor wafers · CPC title

  • characterised by job scheduling, process planning, material flow · CPC title

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What does patent US11157672B1 cover?
One embodiment of the present disclosure provides a system for determining a hybrid-manufacturing plan for manufacturing an integrated circuit (IC). During operation, the system can obtain a set of hybrid-manufacturing constraints for manufacturing the IC. The set of hybrid-manufacturing constraints can include a set of primitives, a set of atoms, and an atom end-state vector. An atom can corre…
Who is the assignee on this patent?
Palo Alto Res Ct Inc
What technology area does this patent fall under?
Primary CPC classification G05B19/41865. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Oct 26 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B1). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).