Faster access of virtual machine memory backed by a host computing device's virtual memory

Patent metadata

Field	Value
Publication number	US-11157306-B2
Application number	US-202017006858-A
Country	US
Kind code	B2
Filing date	Aug 30, 2020
Priority date	Nov 21, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

To increase the speed with which the hierarchical levels of a Second Layer Address Table (SLAT) are traversed as part of a memory access where the guest physical memory of a virtual machine environment is backed by virtual memory assigned to one or more processes executing on a host computing device, one or more hierarchical levels of tables within the SLAT can be skipped or otherwise not referenced. While the SLAT can be populated with memory correlations at hierarchically higher-levels of tables, the page table of the host computing device, supporting the host computing device's provision of virtual memory, can maintain a corresponding contiguous set of memory correlations at the hierarchically lowest table level, thereby enabling the host computing device to page out, or otherwise manipulate, smaller chunks of memory. If such manipulation occurs, the SLAT can be repopulated with memory correlations at the hierarchically lowest table level.

First claim

We claim:

1. A method of increasing a speed of access of computer memory, the method comprising:
detecting a first memory access, from a first process, directed to a first range of memory in a first memory addressing scheme;
generating, as a precondition to completing the first memory access, a first entry in a first hierarchically arranged memory address translation table, the first hierarchically arranged memory address translation table correlating memory addresses between the first memory addressing scheme and a second memory addressing scheme, the first entry being at least one hierarchical level above a hierarchically lowest level of tables such that a second range of memory, identified by the first entry, can be identified without reference to any table in the hierarchically lowest level of tables, the second range of memory being greater than the first range of memory; and
in response to generating the first entry in the first hierarchically arranged memory address translation table, marking as used a first plurality of entries in a second hierarchically arranged memory address translation table, the second hierarchically arranged memory address translation table correlating memory addresses between the second memory addressing scheme and a third memory addressing scheme, the first plurality of entries referencing, in aggregate, the same second range of memory as the first entry in the first hierarchically arranged memory address translation table, wherein entries of the first plurality of entries are at a hierarchically lowest level of tables;
wherein memory addressed by the first memory addressing scheme is backed by memory addressed by the third memory addressing scheme.

2. The method of claim 1 , further comprising:
detecting a second memory access from the first process, the second memory access being directed to a third range of memory that differs from the first range of memory; and
satisfying the second memory access by reference to a second subset of the first plurality of entries in the second hierarchically arranged memory address translation table;
wherein the first memory access was satisfied by reference to a first subset of the first plurality of entries in the second hierarchically arranged memory address translation table, the first subset comprising different entries, in the second hierarchically arranged memory address translation table, than the second subset.

3. The method of claim 1 , further comprising:
detecting, after the first memory access completes, that a first subset of the first plurality of entries in the second hierarchically arranged memory address translation table have had data, that was originally stored in physical memory, subsequently paged out to a non-volatile storage medium;
invalidating, in response to the detecting, the first entry in the first hierarchically arranged memory address translation table; and
generating, in place of the first entry in the first hierarchically arranged memory address translation table, a second plurality of entries in the first hierarchically arranged memory address translation table, the second plurality of entries referencing, in aggregate, at least some of the same second range of memory as the first entry, wherein entries of the second plurality of entries are at a hierarchically lowest level of tables.

4. The method of claim 3 , wherein the second plurality of entries references portions of the second range of memory that were previously accessed by the first process and were not paged out.

5. The method of claim 1 , further comprising:
assembling, within the second memory addressing scheme, a first plurality of contiguous small page sized regions of memory into a single large page sized region of memory.

6. The method of claim 5 , wherein the assembling occurs subsequent to the detecting the first memory access and prior to the generating the first entry in the first hierarchically arranged memory address translation table.

7. The method of claim 5 , further comprising:
generating a second entry in the first hierarchically arranged memory address translation table, the second entry being at the least one hierarchical level above the hierarchically lowest level of tables such that a third range of memory, identified by the second entry, can be identified without reference to any table in the hierarchically lowest level of tables, the third range of memory referencing the single large page sized region of memory into which the first plurality of the contiguous small page sized regions of memory were assembled; and
in response to generating the second entry in the first hierarchically arranged memory address translation table, marking as used a second plurality of entries in the second hierarchically arranged memory address translation table, the second plurality of entries referencing the first plurality of the contiguous small page sized regions of memory which were assembled into the single large page sized region of memory.

8. The method of claim 7 , further comprising:
copying data from a second plurality of small page sized regions of memory to at least a portion of the first plurality of the contiguous small page sized regions, the second plurality of small page sized regions being at least partly discontinuous; and
invalidating a second plurality of entries in the first hierarchically arranged memory address translation table that referenced the second plurality of small page sized regions of memory, wherein entries of the second plurality of entries are at a hierarchically lowest level of tables;
wherein the generated second entry in the first hierarchically arranged memory address translation table is utilized in place of the second plurality of entries that were invalidated.

9. The method of claim 7 , further comprising:
copying data from a second set of one or more small page sized regions of memory to at least a portion of the first plurality of the contiguous small page sized regions; and
invalidating a second plurality of entries in the first hierarchically arranged memory address translation table, the second plurality of entries comprising both: (1) a first subset of entries that reference the second set of the one or more small page sized regions of memory and (2) a second subset of entries that reference at least some of the first plurality of contiguous small page sized regions of memory, wherein entries of the second plurality of entries are at a hierarchically lowest level of tables;
wherein the generated second entry in the first hierarchically arranged memory address translation table is utilized in place of the second plurality of entries that were invalidated.

10. The method of claim 5 , wherein the assembling the first plurality of contiguous small page sized regions of memory comprises copying data from some of the first plurality of contiguous small page sized regions to other small page sized regions of memory that differ from the first plurality of contiguous small page sized regions.

11. The method of claim 10 , wherein the copying the data from the some of the first plurality of contiguous small page sized regions to the other small page sized regions is only performed if a fragmentation of the first plurality of contiguous small page sized regions is below a fragmentation threshold.

12. The method of claim 1 , further comprising:
preventing paging of the second range of memory.

13. The method of claim 12 , wherein the preventing the paging of the second range of memory is only performed if one or more portions of the second range of memory are accessed more frequently than an access frequency threshold.

1

Assignees

• Microsoft Technology Licensing Llc

Inventors

• Bak Yevgeniy
• Iyigun Mehmet
• Kishan Arun U

Classifications

• G06F12/1416

  by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights (G06F12/1458 takes precedence) · CPC title

• G06F2009/45579

  I/O management, e.g. providing access to device drivers or storage · CPC title

• G06F2212/651

  Multi-level translation tables · CPC title

• G06F9/45558 Primary

  Hypervisor-specific management and integration aspects · CPC title

• G06F12/1009 Primary

  using page tables, e.g. page table structures · CPC title