Circuit substrate, display device and driving method

Patent metadata

Field	Value
Publication number	US-11156882-B2
Application number	US-201916394417-A
Country	US
Kind code	B2
Filing date	Apr 25, 2019
Priority date	Apr 27, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

A circuit substrate, a display device and a driving method are provided. The circuit substrate includes a base substrate, a gate driving circuit, and at least one signal trace group which are on the base substrate. The signal trace group includes two signal traces, and the two signal traces are electrically connected with the gate driving circuit and are configured to provide clock signals with inverted phases to the gate driving circuit; the two signal traces are respectively in different layers and are insulated from each other; and orthographic projections of the two signal traces on the base substrate at least partially overlap with each other.

First claim

What is claimed is:

1. A circuit substrate, comprising a base substrate, a gate driving circuit on the base substrate, and a plurality of signal trace groups on the base substrate,
wherein each of the plurality of signal trace groups comprises two signal traces; the two signal traces of each of the plurality of signal trace groups are electrically connected with the gate driving circuit and are configured to provide clock signals with inverted phases to the gate driving circuit; the two signal traces of each of the plurality of signal trace groups are respectively in different layers and are insulated from each other; and orthographic projections of the two signal traces of each of the plurality of signal trace groups on the base substrate at least partially overlap with each other;
wherein the plurality of signal trace groups comprises a first signal trace group and a second signal trace group; at least one of two signal traces of the first signal trace group is on a different layer than two signal traces of the second signal trace group.

2. The circuit substrate according to claim 1 , further comprising a gate insulation layer for a thin film transistor and a passivation layer covering the thin film transistor,
the two signal traces of the first signal trace group are spaced apart from each other by the gate insulation layer so that the two signal traces of the first signal trace group are insulated from each other, and the two signal traces of the second signal trace group are spaced apart from each other by the gate insulation layer so that the two signal traces of the second signal trace group are insulated from each other; or
the two signal traces of the first signal trace group are spaced apart from each other by the passivation layer so that the two signal traces of the first signal trace group are insulated from each other, and the two signal traces of the second signal trace group are spaced apart from each other by the passivation layer so that the two signal traces of the second signal trace group are insulated from each other.

3. The circuit substrate according to claim 2 ,
wherein the two signal traces of the first signal trace group are respectively a first signal trace and a second signal trace, and the two signal traces of the second signal trace group are respectively a third signal trace and a fourth signal trace;
the gate driving circuit comprises a plurality of cascaded shift register units, the first signal trace is electrically connected with a (4m−3)th-stage of the shift register units, the third signal trace is electrically connected with a (4m−2)th-stage of the shift register units, the second signal trace is electrically connected with a (4m−1)th-stage of the shift register units, and the fourth signal trace is electrically connected with a (4m)th-stage of the shift register units, wherein m is an integer greater than or equal to 1.

4. The circuit substrate according to claim 1 , further comprising a gate insulation layer for a thin film transistor and a passivation layer covering the thin film transistor,
wherein the plurality of signal trace groups comprises a first signal trace group and a second signal trace group;
two signal traces of the first signal trace group are spaced apart from each other by the gate insulation layer so that the two signal traces of the first signal trace group are insulated from each other, and two signal traces of the second signal trace group are spaced apart from each other by the passivation layer so that the two signal traces of the second signal trace group are insulated from each other.

5. The circuit substrate according to claim 4 , wherein the gate insulation layer and the passivation layer are between the two signal traces of the second signal trace group.

6. The circuit substrate according to claim 4 , wherein one signal trace of the first signal trace group and one signal trace of the second signal trace group are in a same layer.

7. The circuit substrate according to claim 4 ,
wherein the two signal traces of the first signal trace group are respectively a first signal trace and a second signal trace, and the two signal traces of the second signal trace group are respectively a third signal trace and a fourth signal trace;
the gate driving circuit comprises a plurality of cascaded shift register units, the first signal trace is electrically connected with a (4m−3)th-stage of the shift register units, the third signal trace is electrically connected with a (4m−2)th-stage of the shift register units, the second signal trace is electrically connected with a (4m−1)th-stage of the shift register units, and the fourth signal trace is electrically connected with a (4m)th-stage of the shift register units, wherein m is an integer greater than or equal to 1.

8. The circuit substrate according to claim 1 , further comprising a plurality of touch electrodes,
wherein the plurality of touch electrodes is on the base substrate and arranged in an array.

9. A driving method for the circuit substrate according to claim 1 , comprising:
providing clock signals to the gate driving circuit through the two signal traces; and
providing the clock signals with inverted phases to the gate driving circuit respectively through the two signal traces of each of the plurality of signal trace groups.

10. The driving method according to claim 9 ,
wherein the plurality of signal trace groups comprises a first signal trace group and a second signal trace group; two signal traces of the first signal trace group are respectively a first signal trace and a second signal trace, two signal traces of the second signal trace group are respectively a third signal trace and a fourth signal trace, and the gate driving circuit comprises a plurality of cascaded shift register units;
the driving method further comprises:
providing a clock signal to a (4m−3)th-stage of the shift register units through the first signal trace,
providing another clock signal to a (4m−2)th-stage of the shift register units through the third signal trace,
providing further another clock signal to a (4m−1)th-stage of the shift register units through the second signal trace, and
providing further another clock signal to a (4m)th-stage of the shift register units through the fourth signal trace, wherein m is an integer greater than or equal to 1.

11. A display device, comprising a circuit substrate,
wherein the circuit substrate comprises a base substrate, a gate driving circuit on the base substrate, and a plurality of signal trace groups on the base substrate,
each of the plurality of signal trace groups comprises two signal traces; the two signal traces of each of the plurality of signal trace groups are electrically connected with the gate driving circuit and are configured to provide clock signals with inverted phases to the gate driving circuit; the two signal traces of each of the plurality of signal trace groups are respectively in different layers and are insulated from each other; and orthographic projections of the two signal traces of each of the plurality of signal trace groups on the base substrate at least partially overlap with each other;
wherein at least one of two signal traces of one of the plurality of signal trace groups is on a different layer than two signal traces of another of the plurality of signal trace groups.

12. The display device according to claim 11 , wherein the circuit substrate comprises a plurality of touch electrodes,
and the plurality of touch electrodes are on the base substrate and arranged in an array.

Assignees

• Chongqing Boe Optoelectronics Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Qin Peng
• Zuo Cheng
• Dang Kangpeng
• Rao Yang
• Wang Bo
• Jin Zhong
• Jiang Lihua

Classifications

• G06F3/0412

  Digitisers structurally integrated in a display · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G09G3/3225

  using an active matrix · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G02F1/13338

  Input devices, e.g. touch panels · CPC title