Methods and circuits for adaptive equalization

Patent metadata

Field	Value
Publication number	US-11153133-B2
Application number	US-202017101657-A
Country	US
Kind code	B2
Filing date	Nov 23, 2020
Priority date	May 21, 2004
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

An integrated circuit equalizes a data signal expressed as a series of symbols. The symbols form data patterns with different frequency components. By considering these patterns, the integrated circuit can experiment with equalization settings specific to a subset of the frequency components, thereby finding an equalization control setting that optimizes equalization. Optimization can be accomplished by setting the equalizer to maximize symbol amplitude.

First claim

What is claimed is:

1. An integrated circuit comprising:
an adjustable equalizer to treat an input signal to a range of frequency-dependent amplification factors to thereby produce an equalized signal;
a sampler coupled to the adjustable equalizer to sample the equalized signal in time to a first clock signal of a first frequency to thereby produce a first sequence of samples; and
an amplitude detector coupled to the adjustable equalizer to sample the equalized signal with reference to a threshold and in time to a second clock signal of a second frequency lower than the first frequency to thereby produce a second sequence of samples, the amplitude detector including control logic to adjust the threshold responsive to the second sequence of samples.

2. The integrated circuit of claim 1 , the control logic to adjust the threshold responsive to both the first sequence of samples and the second sequence of samples.

3. The integrated circuit of claim 1 , wherein the threshold is a voltage.

4. The integrated circuit of claim 1 , wherein the first clock signal comprises first edges, the second clock signal comprises second edges, and the integrated circuit further comprising an edge aligner to temporally align the second edges with the first edges.

5. The integrated circuit of claim 1 , the control logic to adjust the frequency-dependent amplification factors responsive to the second sequence of samples.

6. The integrated circuit of claim 5 , the control logic to adjust the frequency-dependent amplification factors responsive to both the first sequence of samples and the second sequence of samples.

7. The integrated circuit of claim 1 , further comprising a filter to detect a high-frequency pattern in the first sequence of samples.

8. The integrated circuit of claim 7 , the control logic to adjust the threshold responsive to the second sequence of samples and the high-frequency pattern in the first sequence of samples.

9. The integrated circuit of claim 1 , the amplitude detector further including a ratio circuit to accumulate the ratio of the second sequence of samples to the first sequence of samples.

10. The integrated circuit of claim 9 , wherein the ratio is the number of samples in the second sequence of samples that exceed the threshold to the number of samples in the first sequence of samples.

11. The integrated circuit of claim 1 , wherein the control logic alters the threshold responsive to changes in the ratio.

12. A method comprising:
treating an input signal to a range of frequency-dependent amplification factors to thereby produce an equalized signal;
sampling the equalized signal in time to a first clock signal of a first frequency to thereby produce a first sequence of samples;
sampling the equalized signal with reference to a threshold and in time to a second clock signal of a second frequency lower than the first frequency to thereby produce a second sequence of samples; and
adjusting the threshold responsive to the second sequence of samples.

13. The method of claim 12 , further comprising adjusting the threshold responsive to the first sequence of samples.

14. The method of claim 12 , wherein the threshold is a voltage.

15. The method of claim 12 , wherein the first clock signal comprises first edges, the second clock signal comprises second edges, and the method further comprises aligning the second edges with the first edges.

16. The method of claim 12 , further comprising adjusting the frequency-dependent amplification factors responsive to the second sequence of samples.

17. The method of claim 16 , further comprising adjusting the frequency-dependent amplification factors responsive to the first sequence of samples.

18. The method of claim 12 , further comprising detecting a high-frequency pattern in the first sequence of samples.

19. The method of claim 18 , further comprising adjusting the threshold responsive to the second sequence of samples and the high-frequency pattern in the first sequence of samples.

20. An integrated circuit comprising:
an adjustable equalizer to treat an input signal to a range of frequency-dependent amplification factors to thereby produce an equalized signal;
a sampler coupled to the adjustable equalizer to sample the equalized signal in time to a first clock signal of a first frequency to thereby produce a first sequence of samples; and
means for sampling the equalized signal with reference to a threshold and in time to a second clock signal of a second frequency lower than the first frequency to thereby produce a second sequence of samples, and for adjusting the threshold responsive to the second sequence of samples.

Assignees

• Rambus Inc

Inventors

• Farjad-Rad Ramin

Classifications

• H04B3/145

  variable equalisers · CPC title

• H04L25/03019 Primary

  adaptive, i.e. capable of adjustment during data reception · CPC title

• H04L25/085

  Arrangements for reducing interference in line transmission systems, e.g. by differential transmission · CPC title

• H04L25/03159 Primary

  operating in the frequency domain (H04L25/03165, H04L25/03178 take precedence) · CPC title

• H04L25/03885

  adaptive · CPC title