Semiconductor device

Patent metadata

Field	Value
Publication number	US-11152922-B2
Application number	US-202016792343-A
Country	US
Kind code	B2
Filing date	Feb 17, 2020
Priority date	Jun 13, 2019
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.

First claim

What is claimed is:

1. A semiconductor device comprising:
a scan input circuit configured to receive configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal;
a master latch configured to latch the first select signal to output a first output signal;
a slave latch configured to latch the first output signal to output a second output signal;
a first inverter configured to invert the second output signal to output a final output signal; and
a scan output circuit configured to receive a signal output from the slave latch and an external signal to output a first scan output signal,
wherein the scan output circuit includes:
a first scan output inverter configured to invert the signal output from the slave latch to output a third output signal, wherein
a ground terminal of the first scan output inverter receives an inverted scan enable signal.

2. The semiconductor device of claim 1 , wherein:
the scan output circuit further includes:
a second scan output inverter configured to invert the third output signal to output a fourth output signal.

3. The semiconductor device of claim 2 , wherein the scan output circuit includes a scan logic operation gate configured to receive the external signal and the fourth output signal and perform a logic operation on the external signal and the fourth output signal to output a scan output signal.

4. The semiconductor device of claim 3 , wherein:
the scan logic operation gate includes a scan output NAND gate; and
the external signal includes the scan enable signal.

5. The semiconductor device of claim 3 , wherein:
the scan logic operation gate includes a scan output NOR gate; and
the external signal includes an inverted scan enable signal.

6. The semiconductor device of claim 1 , wherein:
the scan output circuit further includes:
a second scan output inverter configured to invert the third output signal to output a fourth output signal,
wherein a ground terminal of the second scan output inverter receives the inverted scan enable signal.

7. The semiconductor device of claim 6 , wherein the scan output circuit includes:
a scan output NAND gate configured to receive the external signal and the fourth output signal and perform a logic operation on the external signal and the fourth output signal to output a scan output signal; and
the external signal includes the scan enable signal.

8. The semiconductor device of claim 1 , wherein:
the slave latch includes a second inverter;
the second inverter inverts the second output signal,
the signal output from the slave latch is an output of the second inverter,
the external signal is an scan enable signal.

9. The semiconductor device of claim 8 , wherein the scan output circuit further includes:
a second scan output inverter configured to invert the third output signal to output a fourth output signal,
wherein ground terminals of the second scan output inverter receive the scan enable signal.

10. A semiconductor device comprising:
a first scan input circuit configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal;
a first master latch configured to latch the first select signal to output a first output signal;
a first slave latch configured to latch the first output signal to output a second output signal, wherein the first slave latch includes a first inverter, and the first inverter inverts the second output signal to output a third output signal;
a second scan input circuit configured to receive the third output signal, a second data signal, and the scan enable signal and select any one of the second data signal and the third output signal in response to the scan enable signal to output a second select signal;
a second master latch configured to latch the second select signal to output a fourth output signal;
a second slave latch configured to latch the fourth select signal to output a fifth output signal; and
a scan output circuit configured to receive a signal output from the second slave latch and an external signal to output a first scan output signal.

11. The semiconductor device of claim 10 , wherein:
the scan output circuit includes:
a first scan output inverter configured to invert the fifth output signal to output a sixth output signal; and
a second scan output inverter configured to invert the sixth output signal to output a seventh output signal,
wherein ground terminals of the first scan output inverter and the second scan output inverter receive an inverted scan enable signal.

12. The semiconductor device of claim 11 , wherein:
the scan output circuit includes a scan output NAND gate configured to receive the external signal and the seventh output signal and perform a logic operation on the external signal and the seventh output signal to output a scan output signal; and
the external signal includes the scan enable signal.

13. The semiconductor device of claim 11 , wherein:
the scan output circuit includes a scan output NOR gate configured to receive the external signal and the seventh output signal and perform a logic operation on the external signal and the seventh output signal to output a scan output signal; and
the external signal includes the inverted scan enable signal.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim San Ha
• Shin Taek Kyun
• Kim Min Su

Classifications

• H03K19/20 Primary

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G01R31/318371

  Methodologies therefor, e.g. algorithms, procedures · CPC title

• G01R31/318541

  Scan latches or cell details · CPC title

• H03K3/0372 Primary

  of the primary-secondary type · CPC title

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title