System and method for managing requests in an asynchronous pipeline

Patent metadata

Field	Value
Publication number	US-11151287-B2
Application number	US-201816213500-A
Country	US
Kind code	B2
Filing date	Dec 7, 2018
Priority date	Dec 7, 2018
Publication date	Oct 19, 2021
Grant date	Oct 19, 2021

Abstract

An asynchronous pipeline circuit includes: a first processing stage including a first data latch configured to generate a request signal; a second processing stage downstream the first processing stage and including a second data latch; and a programmable delay line coupled between the first data latch and the second processing stage. The programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal on each data transfer from the first data latch to the second data latch.

First claim

What is claimed is:

1. An asynchronous pipeline circuit, comprising:
a first processing stage comprising a first data latch, the first data latch configured to generate a request signal;
a second processing stage downstream the first processing stage, the second processing stage comprising a second data latch;
a data transfer line for transferring data from the first processing stage to the second processing stage, the data transfer line coupled between the first processing stage and the second processing stage; and
a programmable delay line coupled between the first data latch and the second data latch different from the data transfer line, wherein the programmable delay line is configured to receive the request signal from the first data latch and to generate a delayed request signal by randomly delaying the request signal from the first data latch to the second data latch for each data transferred along the data transfer line.

2. The asynchronous pipeline circuit of claim 1 , wherein the second processing stage is configured to receive the delayed request signal and to provide an acknowledgment signal to the first processing stage in response to reception of the delayed request signal from the programmable delay line and in response to reception of data from the first data latch.

3. The asynchronous pipeline circuit of claim 2 , wherein the first processing stage further comprises a first controller, and wherein the second data latch is configured to provide the acknowledgment signal to the first controller.

4. The asynchronous pipeline circuit of claim 3 , wherein the programmable delay line is configured to provide the delayed request signal to the second data latch.

5. The asynchronous pipeline circuit of claim 2 , wherein each of the first processing stage and the second processing stage comprises a respective Muller C-element, and wherein each of the first data latch and the second data latch comprises a respective capture-pass latch.

6. The asynchronous pipeline circuit of claim 5 , wherein the programmable delay line is configured to provide the delayed request signal to the Muller C-element of the second processing stage.

7. The asynchronous pipeline circuit of claim 5 , wherein the acknowledgment signal is configured to be passed from a control output of the capture-pass latch of the second processing stage to a pass input of the capture-pass latch of the first processing stage.

8. The asynchronous pipeline circuit of claim 1 , further comprising a random number generator configured to generate a random number and to provide the random number to the programmable delay line.

9. The asynchronous pipeline circuit of claim 8 , wherein the programmable delay line is configured to add a random delay to the request signal based on the random number to generate the delayed request signal.

10. The asynchronous pipeline circuit of claim 1 , further comprising a delay element coupled between the first data latch and the programmable delay line, wherein the delay element is separate from the programmable delay line.

11. The asynchronous pipeline circuit of claim 10 wherein the asynchronous pipeline circuit further comprises combinatorial logic circuitry coupled between the first data latch and the second data latch.

12. An asynchronous pipeline circuit, comprising:
a first processing stage comprising:
a first data latch configured to receive data and to generate a request signal; and
a first controller configured to control outputting of the data from the first data latch;
a second processing stage comprising:
a second data latch configured to receive the data from the first data latch; and
a second controller configured to control outputting of the data from the second data latch;
a data transfer line for transferring data from the first processing stage to the second processing stage, the data transfer line coupled between the first processing stage and the second processing stage;
a programmable delay line coupled between the first processing stage and the second processing stage different from the data transfer line, wherein the programmable delay line is configured to receive the request signal from the first data latch and to generate a randomly-delayed request signal by delaying the request signal by a random time from the first data latch to the second data latch for each data transferred along the data transfer line; and
a random number generator configured to generate a random number, wherein the programmable delay line is configured to randomly delay the request signal based on the random number.

13. The asynchronous pipeline circuit of claim 12 , wherein the second processing stage is configured to receive the randomly-delayed request signal and to provide an acknowledgment signal to the first processing stage in response to reception of the randomly-delayed request signal from the programmable delay line and in response to reception of data from the first data latch.

14. The asynchronous pipeline circuit of claim 12 , wherein each of the first data latch and the second data latch comprises a D-latch, and wherein each of the first controller and the second controller comprises a logic gate.

15. The asynchronous pipeline circuit of claim 14 , wherein the logic gate comprises an exclusive NOR gate.

16. The asynchronous pipeline circuit of claim 12 , wherein each of the first data latch and the second data latch comprises a capture-pass latch, and wherein each of the first controller and the second controller comprises a two-input Muller C-element.

17. The asynchronous pipeline circuit of claim 12 , wherein the random time is between 0.1 ns and 3.2 ns.

18. A method for managing requests in an asynchronous pipeline circuit, the method comprising:
generating, by a first data latch of a first processing stage of the asynchronous pipeline circuit, a request signal;
delaying, by a programmable delay line, the request signal by a random delay;
receiving the randomly-delayed request signal at a second processing stage downstream the first processing stage, the second processing stage comprising a second data latch; and
providing, by the second processing stage, an acknowledgment signal to the first processing stage in response to reception of the randomly-delayed request signal and in response to reception of data from the first data latch, wherein the delaying occurs from the first data latch to the second data latch at each data transfer along a data transfer line different from the programmable delay line.

19. The method of claim 18 , wherein the random delay is in steps of 0.1 ns.

20. The method of claim 18 , wherein the random delay is between 0.1 ns and 3.2 ns.

Assignees

• St Microelectronics Sa
• Inst Polytechnique Grenoble

Inventors

• Germain Sophie
• Engels Sylvain
• Fesquet Laurent

Classifications

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F21/755

  with measures against power attack · CPC title

• H03K19/20

  characterised by logic function, e.g. AND, OR, NOR, NOT circuits (H03K19/003 - H03K19/01 take precedence) · CPC title

• G06F21/77

  in smart cards · CPC title

• H03K5/14 Primary

  by the use of delay lines (H03K5/133 takes precedence) · CPC title