Method of controlling placement of micro-objects

US11148941B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11148941-B2
Application numberUS-201816237316-A
CountryUS
Kind codeB2
Filing dateDec 31, 2018
Priority dateDec 31, 2018
Publication dateOct 19, 2021
Grant dateOct 19, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler.

First claim

Opening claim text (preview).

What is claimed is: 1. A method, comprising: depositing a set of micro-objects onto a surface of a micro-assembler, wherein the micro-assembler comprises a two-dimensional array of force generating pixels; and manipulating the set of micro-objects individually on the surface of the micro-assembler using a set of control patterns simultaneously, wherein each control pattern of the set of control patterns indicates a force pattern on a portion of the two-dimensional array of force generating pixels, and wherein manipulating the set of micro-objects comprises controlling orientations of the set of micro-objects in three dimensions relative to the surface of the micro-assembler. 2. The method of claim 1 , wherein each control pattern of the set of control patterns further indicates a center position and an orientation for a respective force pattern. 3. The method of claim 1 , wherein each control pattern of the set of control patterns is determined based on one or more of: user input provided by a user of the micro-assembler; an analysis of the set of micro-objects performed by a computing device; and a pre-determined order or timing for the set of control patterns. 4. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: moving the set of micro-objects across the surface of the micro-assembler relative to one or more of a reference structure or a second set of micro-objects, using the set of control patterns. 5. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: rotating the set of micro-objects with respect to the surface of the micro-assembler or relative to one or more of a reference structure or a second set of micro-objects, using the set of control patterns. 6. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: distributing the set of micro-objects to random locations on the surface of the micro-assembler, using the set of control patterns. 7. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: concentrating the set of micro-objects in an area on the surface of the micro-assembler, using the set of control patterns. 8. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: deconcentrating the set of micro-objects from an area on the surface of the micro-assembler, using the set of control patterns. 9. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: holding the set of micro-objects in an area of the surface of the micro-assembler to resist one or more forces which may include one or more of shear forces, drag forces, electrophoretic forces or dielectrophoretic forces, electroosmotic forces, using the set of control patterns. 10. The method of claim 1 , further comprising: manipulating a second set of micro-objects on the surface of the micro-assembler using a second set of control patterns, wherein manipulating the set of micro-objects and manipulating the second set of micro-objects occur simultaneously. 11. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: forming the set of micro-objects into a pattern on the surface of the micro-assembler. 12. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: manipulating a first subset of the set of micro-objects and a second subset of set of micro-objects simultaneously. 13. The method of claim 1 , wherein manipulating the set of micro-objects on the surface of the micro-assembler comprises: manipulating the set of micro-objects using different subsets of the set of control patterns over different periods of time, wherein each subset of the set of control patterns is used during a respective period of time.

Assignees

Inventors

Classifications

  • B81C99/002Primary

    Apparatus for assembling MEMS, e.g. micromanipulators (micromanipulators per se B25J7/00) · CPC title

  • Regular or irregular arrays of nanoscale structures, e.g. etch mask layer (photomechanical, e.g. photolithographic, production of textured or patterned surfaces G03F7/00; lithographic processes for making patterned surfaces using printing and stamping G03F7/0002) · CPC title

  • of static structures · CPC title

  • Manufacture or treatment of nanostructures · CPC title

  • Forming nanoscale microstructures using auto-arranging or self-assembling material · CPC title

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What does patent US11148941B2 cover?
Disclosed are methods and systems of controlling the placement of micro-objects on the surface of a micro-assembler. Control patterns may be used to cause phototransistors or electrodes of the micro-assembler to generate dielectrophoretic (DEP) and electrophoretic (EP) forces which may be used to manipulate, move, position, or orient one or more micro-objects on the surface of the micro-assembler.
Who is the assignee on this patent?
Palo Alto Res Ct Inc
What technology area does this patent fall under?
Primary CPC classification B81C99/002. Mapped technology areas include Operations & Transport.
When was this patent published?
Publication date Tue Oct 19 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).