Array substrate and method for fabricating the same, display panel, display device

Patent metadata

Field	Value
Publication number	US-11145682-B2
Application number	US-201916621325-A
Country	US
Kind code	B2
Filing date	Mar 13, 2019
Priority date	Mar 23, 2018
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

An array substrate which includes a display region and a peripheral region surrounding the display region, the peripheral region includes a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region; the driving circuit region includes a driving circuit, the data line lead region includes a the plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit; and the data line lead region includes peripheral data line leads, a region of the peripheral region close to the peripheral data line leads includes at least one retaining wall configured to prevent plasma from affecting the peripheral data line leads. A method for fabricating an array substrate, a display panel, and a display device are also disclosed.

First claim

What is claimed is:

1. An array substrate, comprising a display region and a peripheral region surrounding the display region,
wherein the peripheral region comprises a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region;
wherein the driving circuit region comprises a driving circuit, the data line lead region comprises a plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit; and
wherein the data line lead region comprises peripheral data line leads, a region of the peripheral region close to the peripheral data line leads comprises at least one retaining wall configured to prevent plasma from affecting the peripheral data line leads, and an orthographic projection of the at least one retaining wall on the array substrate and an orthographic projection of the plurality of data line leads and the peripheral data line leads on the array substrate do not overlap.

2. The array substrate of claim 1 , wherein the at least one retaining wall comprises two retaining walls which are arranged oppositely.

3. The array substrate of claim 1 , further comprising a base substrate and an interlayer dielectric layer on a side of the base substrate,
wherein the retaining wall is arranged in a same layer and made of a same material as the interlayer dielectric layer, and a height of the retaining wall in a direction perpendicular to the base substrate is larger than a height of the interlayer dielectric layer in the direction perpendicular to the base substrate.

4. The array substrate of claim 3 , wherein the data line leads are arranged on a surface of the interlayer dielectric layer away from the base substrate, and the height of the retaining wall in the direction perpendicular to the base substrate is not smaller than a sum of the height of the interlayer dielectric layer and a height of the data line leads in the direction perpendicular to the base substrate.

5. The array substrate of claim 3 , further comprising a dummy SD, wherein the dummy SD is arranged on a side of the interlayer dielectric layer away from the base substrate, and the dummy SD is between the retaining wall and the data line leads.

6. The array substrate of claim 5 , wherein a space between the retaining wall and the dummy SD equals to a space between the data line leads.

7. The array substrate of claim 5 , wherein a space between the retaining wall and the dummy SD is about 2.0 μm˜2.5 μm.

8. The array substrate of claim 1 , further comprising a base substrate, an interlayer dielectric layer on a side of the base substrate, and a gate layer between the base substrate and the interlayer dielectric layer, wherein the retaining wall is arranged in a same layer and made of a same material as the gate layer, and a sum of a height of the interlayer dielectric layer and a height of the retaining wall in the direction perpendicular to the base substrate is larger than a sum of the height of the interlayer dielectric layer and a height of the gate layer in the direction perpendicular to the base substrate.

9. The array substrate of claim 1 , further comprising a base substrate, and a gate insulating layer, a gate layer, and an interlayer dielectric layer which are arranged away from the base substrate in this order, wherein the retaining wall is arranged in a same layer and made of a same material as the gate insulating layer, and a sum of a height of the interlayer dielectric layer, a height of the gate layer, and a height of the retaining wall in the direction perpendicular to the base substrate is larger than a sum of the height of the interlayer dielectric layer, the height of the gate layer, and a height of the gate insulating layer in the direction perpendicular to the base substrate.

10. The array substrate of claim 1 , further comprising a base substrate, and a light shield layer, a gate insulating layer, a gate layer, and an interlayer dielectric layer which are arranged away from the base substrate in this order, wherein the retaining wall is arranged in a same layer and made of a same material as the light shield layer, and the sum of a height of the interlayer dielectric layer, a height of the gate layer, a height of the gate insulating layer and a height of the retaining wall perpendicular to the base substrate is larger than the sum of the height of the interlayer dielectric layer, the height of the gate layer, the height of the gate insulating layer, and a height of the light shield layer perpendicular to the base substrate.

11. The array substrate of claim 1 , wherein the retaining wall has a width of about 2.5 μm˜20 μm.

12. The array substrate of claim 1 , wherein the retaining wall has a width of about 2.5 μm, and the data line leads have a width of 2.5 μm.

13. A display panel, comprising the array substrate of claim 1 .

14. A display device, comprising the array substrate of claim 1 .

15. A method for fabricating an array substrate,
wherein the array substrate comprises a display region and a peripheral region surrounding the display region,
wherein the peripheral region comprises a data line lead region and a driving circuit region, and the data line lead region is between the driving circuit region and the display region;
wherein the driving circuit region comprises a driving circuit, the data line lead region comprises a plurality of data line leads, and the plurality of data line leads extend from the display region and are electrically connected with the driving circuit;
wherein the data line lead region comprises peripheral data line leads, and the method comprises: forming at least one retaining wall in a region of the peripheral region close to the peripheral data line leads, wherein the at least one retaining wall is configured to prevent plasma from affecting the peripheral data line leads, and an orthographic projection of the at least one retaining wall on the array substrate and an orthographic projection of the plurality of data line leads and the peripheral data line leads on the array substrate do not overlap.

16. The method of claim 15 , wherein the step of forming at least one retaining wall in the region of the peripheral region close to the peripheral data line leads comprises: forming two retaining walls which are arranged oppositely, in the region of the peripheral region close to the peripheral data line leads.

17. The method of claim 15 , wherein the step of forming at least one retaining wall in the region of the peripheral region close to the peripheral data line leads comprises:
preparing a base substrate,
forming an interlayer dielectric thin film on the base substrate, and
patterning the interlayer dielectric thin film by using a half tone mask, to form the retaining wall and an interlayer dielectric layer, wherein a height of the retaining wall in a direction perpendicular to the base substrate is larger than a height of the interlayer dielectric layer in the direction perpendicular to the base substrate.

18. The method of claim 17 , further comprising:
forming the data line leads on a surface of the interlayer dielectric layer away from the base substrate, wherein the height of the retaining wall in the direction perpendicular to the base substrate is not smaller than a sum of the height of the interlayer dielectric layer and a height of the data line leads in the direction perpendicular to the base substrate.

19. The method of claim 15 , the step of fo

Assignees

• Ordos Yuansheng Optoelectronics Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yu Yanan
• Xu Jingyi
• Ren Yanwei
• Zhao Xin
• Wang Xiaokang
• Wang Yuelin
• Zhang Huijie

Classifications

• H10D86/451 Primary

  characterised by the compositions or shapes of the interlayer dielectrics · CPC title

• H10D86/0231

  using masks, e.g. half-tone masks · CPC title

• H10D30/6723

  having light shields · CPC title

• H10D86/443 Primary

  adapted for preventing breakage, peeling or short circuiting · CPC title

• H10D86/60 Primary

  wherein the TFTs are in active matrices · CPC title