Efficient performance monitoring of integrated circuit(s) having distributed clocks

Patent metadata

Field	Value
Publication number	US-11144087-B2
Application number	US-201916351319-A
Country	US
Kind code	B2
Filing date	Mar 12, 2019
Priority date	Aug 10, 2018
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

Performance monitors are placed on computational units in different clock domains of an integrated circuit. A central dispatcher generates trigger signals to the performance monitors to cause the performance monitors to respond to the trigger signals with packets reporting local performance counts for the associated computational units. The data in the packets are correlated into a single clock domain. By applying a trigger and reporting system, the disclosed approach can synchronize the performance metrics of the various computational units in the different clock domains without having to route a complex global clock reference signal to all of the performance monitors.

First claim

What is claimed is:

1. An integrated circuit device comprising:
a plurality of clock domains each with a corresponding local clock;
a plurality of performance monitors each operating in a different clock domain; and
a central dispatcher coupled to a reference clock, the central dispatcher configured to:
broadcast a trigger signal to the plurality of performance monitors,
form a reference packet indicating when the central dispatcher broadcasted the trigger signal to the plurality of performance monitors, wherein the reference packet includes a first identification of the trigger signal and a reference clock value from the reference clock, and
save the reference packet in a memory,

wherein each of the performance monitors is adapted to:
respond to the trigger signal by forming a return packet to be saved in the memory; and
respond to the trigger signal by resetting one or more local performance counts; and

wherein the clock domains in which the plurality of performance monitors operate are correlated based on the return packets saved in the memory and the reference clock value included in the reference packet saved in the memory.

2. The integrated circuit device of claim 1 , further comprising a router configured to:
perform data reduction on the return packets from the performance monitors to form at least one aggregated return packet; and
save the at least one aggregated return packet in the memory.

3. The integrated circuit device of claim 1 , wherein each return packet
includes: a local clock value based on the corresponding local clock;
a second identification of the trigger signal; and
a local performance count.

4. The integrated circuit device of claim 3 , wherein the first identification and the second identification are the same, the first identification being generated by the central dispatcher, and the second identification being generated by at least one of the performance monitors.

5. The integrated circuit device of claim 1 , wherein the central dispatcher is further configured to receive a command.

6. The integrated circuit device of claim 5 , wherein the command is one of a broadcast a trigger signal command, a start broadcasting trigger signals periodically command, or a stop periodic broadcasting of trigger signals command.

7. The integrated circuit device of claim 1 , wherein the first identification of the trigger signal indicates a total number of trigger signals broadcast by the central dispatcher.

8. The integrated circuit device of claim 1 , wherein the reference packet further includes a bookmark received by the central dispatcher.

9. The integrated circuit device of claim 1 , wherein the reference packet further includes a local clock value for the central dispatcher.

10. The integrated circuit device of claim 1 , wherein the trigger signal comprises a binary level or edge trigger that can be transmitted on a single wire.

11. The integrated circuit device of claim 1 , wherein the integrated circuit device is a graphics processing unit.

12. A method comprising:
broadcasting a trigger signal from a central dispatcher with access to a reference clock to a plurality of performance monitors each operating in a clock domain of a corresponding local clock;
saving, in a memory, a reference packet indicating when the central dispatcher broadcasted the trigger signal to the plurality of performance monitors, the reference packet comprising a first identification of the trigger signal and a reference clock value based on the reference clock; and
for each of the performance monitors, responding to the trigger signal by forming a return packet to be saved in the memory and responding to the trigger signal by resetting one or more local performance count values,
wherein clock domains in which the plurality of performance monitors operate are correlated based on the return packet of each performance monitor saved in the memory and the reference clock value included in the reference packet saved in the memory.

13. The method of claim 12 , wherein each return packet includes:
a local clock value based on the corresponding local clock;
a second identification of the trigger signal; and
a local performance count.

14. The method of claim 13 , wherein the first identification and the second identification are the same, the first identification being generated by the central dispatcher and the second identification being generated by at least one of the performance monitors.

15. The method of claim 12 , further comprising:
receiving a command, wherein the command is one of a broadcast a trigger signal command, a start broadcasting trigger signals periodically command, or a stop periodic broadcasting of trigger signals command.

16. The method of claim 12 , wherein the first identification of the trigger signal indicates a total number of broadcasts of trigger signals.

17. The method of claim 12 , wherein the reference packet further includes a bookmark.

18. The method of claim 12 , wherein the reference packet further includes a local clock value for the central dispatcher.

19. The method of claim 12 , wherein the trigger signal comprises a binary level or edge trigger that can be transmitted on a single wire.

20. The method of claim 12 , wherein the performance monitors are in a central processing unit.

Assignees

• Nvidia Corp

Inventors

• Allen Roger
• Menezes Alan
• Ogletree Tom
• Kamalapurkar Shounak
• Ranade Abhijat

Classifications

• G06F1/12 Primary

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• H04L43/065 Primary

  related to network devices · CPC title

• G06F11/3013

  where the computing system is an embedded system, i.e. a combination of hardware and software dedicated to perform a certain function in mobile devices, printers, automotive or aircraft systems (testing or monitoring of control systems or parts thereof G05B23/02) · CPC title

• G06F9/4887

  involving deadlines, e.g. rate based, periodic · CPC title

• G06F11/3419

  by assessing time · CPC title