Chirp linearity detector for radar

Patent metadata

Field	Value
Publication number	US-11143746-B2
Application number	US-201815999181-A
Country	US
Kind code	B2
Filing date	Aug 17, 2018
Priority date	Feb 27, 2018
Publication date	Oct 12, 2021
Grant date	Oct 12, 2021

Abstract

A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.

First claim

What is claimed is:

1. A chirp linearity detector comprising:
a frequency sampling circuit; and
a frequency sweep linearity measuring circuit, the frequency sweep linearity measuring circuit coupled to the frequency sampling circuit, the frequency sampling circuit comprising:
a programmable-divisor frequency divider circuit for receiving a frequency source output signal from a frequency source, for performing frequency division according to a programmable divisor value, and for providing a frequency divided output signal;
a first low pass filter circuit coupled to the programmable-divisor frequency divider circuit, the first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal;
a mixer circuit coupled to the first low pass filter circuit, the mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal;
a second low pass filter circuit coupled to the mixer circuit, the second low pass filter circuit for receiving the mixer output signal, for performing anti-aliasing filtering, and for providing an analog-to-digital converter (ADC) input signal; and
an ADC circuit coupled to the second low pass filter circuit, the ADC circuit for receiving the ADC input signal, for digitizing the ADC input signal, and for providing a digital output signal.

2. The chirp linearity detector of claim 1 , wherein the frequency sweep linearity measuring circuit comprises:
a digital filter circuit coupled to the ADC circuit, the digital filter circuit for receiving the digital output signal and for detecting frequencies of a swept frequency chirp.

3. The chirp linearity detector of claim 1 , wherein the frequency sweep linearity measuring circuit compares relationships of the frequencies of the swept frequency chirp to measure a linearity of the swept frequency chirp.

4. The chirp linearity detector of claim 1 , wherein the frequency sweep linearity measuring circuit provides a warning indication when comparison of the relationships of the frequencies of the swept frequency chirp indicates nonlinearity of the swept frequency chirp.

5. The chirp linearity detector of claim 1 , wherein a radar using the swept frequency chirp is configured to disregard radar returns arising from the swept frequency chirp when the frequency sweep linearity measuring circuit provides the warning indication.

6. The chirp linearity detector of claim 1 , wherein a local oscillator frequency of the local oscillator signal is configured to provide non-overlapping harmonic bands in the mixer output signal.

7. The chirp linearity detector of claim 1 , wherein the programmable-divisor frequency divider circuit comprises:
a duty cycle adjustment circuit coupled to the programmable-divisor frequency divider for providing a 50% duty cycle for the frequency divided output signal.

8. A method comprising:
receiving a phase locked loop (PLL) output signal from a PLL;
adjusting a frequency divisor in accordance with an analog-to-digital converter (ADC) input frequency range of an ADC;
dividing the PLL output signal according to the frequency divisor to provide a frequency divided output signal;
reducing harmonic mixing using a first low pass filter circuit to produce a mixer input signal;
mixing the mixer input signal with a local oscillator (LO) signal to provide a mixer output signal;
performing anti-aliasing filtering using a second low pass filter circuit to provide an analog-to-digital converter (ADC) input signal; and
digitizing, at an ADC circuit, the ADC input signal to provide a digital output signal.

9. The method of claim 8 , further comprising:
digitally filtering the digital output signal to detect frequencies of a swept frequency chirp.

10. The method of claim 8 , further comprising:
comparing relationships of the frequencies of the swept frequency chirp to measure a linearity of the swept frequency chirp.

11. The method of claim 8 , further comprising:
providing a warning indication when comparison of the relationships of the frequencies of the swept frequency chirp indicates nonlinearity of the swept frequency chirp.

12. The method of claim 8 , further comprising:
causing a radar using the swept frequency chirp to disregard radar returns arising from the swept frequency chirp when the frequency sweep linearity measuring circuit provides the warning indication.

13. The method of claim 8 , further comprising:
configuring a local oscillator frequency of the local oscillator signal to provide non-overlapping harmonic bands in the mixer output signal.

14. The method of claim 8 , wherein the dividing the PLL output signal to provide a frequency divided output signal comprises:
performing frequency division according to a programmable divisor value; and
providing a 50% duty cycle for the frequency divided output signal.

15. An integrated circuit comprising:
a phase-locked loop (PLL) frequency sampling circuit; and
a frequency sweep linearity measuring circuit, the frequency sweep linearity measuring circuit coupled to the PLL frequency sampling circuit, the PLL frequency sampling circuit comprising:
a programmable-divisor frequency divider circuit for receiving a PLL output signal from a PLL, for performing frequency division according to a programmable divisor value, and for providing a frequency divided output signal;
a first low pass filter circuit coupled to the programmable-divisor frequency divider circuit, the first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal;
a mixer circuit coupled to the first low pass filter circuit, the mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal;
a second low pass filter circuit coupled to the mixer circuit, the second low pass filter circuit for receiving the mixer output signal, for performing anti-aliasing filtering, and for providing an analog-to-digital converter (ADC) input signal; and
an ADC circuit coupled to the second low pass filter circuit, the ADC circuit for receiving the ADC input signal, for digitizing the ADC input signal, and for providing a digital output signal.

16. The integrated circuit of claim 15 , wherein the frequency sweep linearity measuring circuit comprises:
a digital filter circuit coupled to the ADC circuit, the digital filter circuit for receiving the digital output signal and for detecting frequencies of a swept frequency chirp.

17. The integrated circuit of claim 15 , wherein the frequency sweep linearity measuring circuit compares relationships of the frequencies of the swept frequency chirp to measure a linearity of the swept frequency chirp.

18. The integrated circuit of claim 15 , wherein the frequency sweep linearity measuring circuit provides a warning indication when comparison of the relationships of the frequencies of the swept frequency chirp indicates nonlinearity of the swept frequency chirp.

19. The integrated circuit of claim 15 , wherein a radar using the swept frequency chirp is configured to disregard radar returns arising from the swept frequency chirp when the frequency sweep linearity measuring circuit provides the warning indication.

20. The integrated circuit of claim 15 , wherein a local oscillator frequency of the local oscillator signal is c

Assignees

• Nxp Usa Inc

Inventors

• Vigier Jean-Stéphane
• Delbecq Dominique
• Pavao-Moreira Cristian
• Barrilado-Gonzalez Andres

Classifications

• G01S7/4017

  of HF systems · CPC title

• G01S7/032

  Constructional details for solid-state radar subsystems · CPC title

• H03L7/0805

  the loop being adapted to provide an additional control signal for use outside the loop · CPC title

• G01S7/4008

  of transmitters · CPC title

• G01S7/4056 Primary

  specially adapted to FMCW · CPC title