Array substrate and fabrication method thereof, and display device

Patent metadata

Field	Value
Publication number	US-11137652-B2
Application number	US-201715769591-A
Country	US
Kind code	B2
Filing date	Oct 19, 2017
Priority date	Mar 27, 2017
Publication date	Oct 5, 2021
Grant date	Oct 5, 2021

Abstract

An array substrate and a fabrication method thereof, and a display device are provided. In the array substrate the pixel units includes common electrode, and the common electrodes of adjacent pixel units in the column direction is electrically connected through a first connection portion; the first signal line is located between the adjacent pixel units in the column direction. A total area of the first connection portion between the common electrodes of every two of the pixel units overlapping with the first signal line is a first overlapping area, at least one end of the first signal line is a first signal input end, and the first overlapping areas decrease as minimum distances from the first connection portions to the first signal input end increase in the row direction.

First claim

The invention claimed is:

1. An array substrate, comprising:
a base substrate;
a plurality of pixel units, arranged in a matrix in a row direction and a column direction; each of the pixel units including a common electrode, and the common electrodes of adjacent pixel units in the column direction being electrically connected through a first connection portion;
a first signal line, located on the base substrate and extending in the row direction, and located between the adjacent pixel units in the column direction, the first connection portion and the first signal line at least partially overlapping with each other,
wherein, a total area of the first connection portion between the common electrodes of every two of the pixel units overlapping with the first signal line is a first overlapping area, at least one end of the first signal line is a first signal input end, and the first overlapping areas decrease as minimum distances from the first connection portions to the first signal input end increase in the row direction, so that coupling capacitances between the first signal line and the first connection portions decrease as minimum distances from the first connection portions to the first signal input end increase in the row direction,
wherein the coupling capacitance between the first signal line and the first connection portion is C=K2·Sm, where K2 is a constant which is related to a dielectric constant and a vertical distance between the first connection portion and the first signal line, and Sm is an area of the first overlapping area.

2. The array substrate according to claim 1 , wherein, the first overlapping area is inversely proportional to the minimum distance from the first connection portion to the first signal input end in the row direction.

3. The array substrate according to claim 1 , further comprising:
a second signal line, located on the base substrate and extending in the column direction, and located between the adjacent pixel units in the row direction;
a second connection portion, configured to connect the common electrodes of adjacent pixel units in the row direction, the second connection portion and the second signal line at least partially overlapping with each other,
wherein, a total area of the second connection portion between the common electrodes of every two of the pixel units overlapping with the second signal line is a second overlapping area, at least one end of the second signal line is a second signal input end, and the second overlapping areas decrease as minimum distances of the second connection portions to the second signal input end increase in the column direction.

4. The array substrate according to claim 3 , wherein, one of the first signal line and the second signal line is a gate line, and the other is a data line.

5. The array substrate according to claim 3 , wherein, a material of the common electrode is the same as a material of at least one of the first connection portion or the second connection portion.

6. The array substrate according to claim 3 , wherein, at least one of the first connection portion or the second connection portion between the common electrodes of at least one pair of pixel units includes a plurality of sub-connection portions.

7. The array substrate according to claim 3 , wherein, in the column direction, the second overlapping area is inversely proportional to the minimum distance of the second connection portion to the second signal input end.

8. A display device, comprising the array substrate according to claim 1 .

9. A fabrication method of an array substrate, comprising:
defining a plurality of pixel units on a base substrate, the plurality of pixel units being arranged in a matrix in a row direction and a column direction, and each of the pixel units including a common electrode;
forming a first connection portion between the common electrodes of adjacent pixel units in the column direction to connect the common electrodes of the adjacent pixel units;
forming a first signal line extending in the row direction on the base substrate, and the first signal line being between the adjacent pixel units in the column direction, the first connection portion and the first signal line at least partially overlapping with each other,
wherein, a total area of the first connection portion between the common electrodes of every two of the pixel units overlapping with the first signal line is a first overlapping area, at least one end of the first signal line is a first signal input end, and the first overlapping areas decrease as minimum distances from the first connection portions to the first signal input end increase in the row direction, so that coupling capacitances between the first signal line and the first connection portions decrease as minimum distances from the first connection portions to the first signal input end increase in the row direction,
wherein the coupling capacitance between the first signal line and the first connection portion is C=K2·Sm, where K2 is a constant which is related to a dielectric constant and a vertical distance between the first connection portion and the first signal line, and Sm is an area of the first overlapping area.

10. The fabrication method of the array substrate according to claim 9 , further comprising:
forming a second signal line extending in the column direction on the base substrate, and forming the second signal line between the adjacent pixel units in the row direction;
forming a second connection portion between common electrodes of the adjacent pixel units in the row direction to connect the common electrodes of the adjacent pixel units, the second connection portion and the second signal line at least partially overlapping with each other,
wherein, a total area of the second connection portion between common electrodes of every two of the pixel units overlapping with the second signal line is a second overlapping area, at least one end of the second signal line is a second signal input end, and the second overlapping areas decrease as minimum distances of the second connection portions to the second signal input end increase in the column direction.

11. The fabrication method of the array substrate according to claim 10 , wherein, at least one of the first connection portion or the second connection portion is formed with the common electrodes by one patterning process.

Assignees

• Boe Technology Group Co Ltd
• Hefei Boe Optoelectronics Tech

Inventors

• Gong Kui
• Duan Xianxue
• Xu Dezhi

Classifications

• G02F1/136286 Primary

  Wiring, e.g. gate line, drain line · CPC title

• G02F1/134309

  characterised by their geometrical arrangement · CPC title

• G02F2201/121

  common or background · CPC title

• G02F1/134318

  having a patterned common electrode · CPC title

• G02F1/1362 Primary

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title