Self-heating effect apparatus and test method

Patent metadata

Field	Value
Publication number	US-11137440-B2
Application number	US-201715853131-A
Country	US
Kind code	B2
Filing date	Dec 22, 2017
Priority date	Dec 23, 2016
Publication date	Oct 5, 2021
Grant date	Oct 5, 2021

Abstract

A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. The devices include a device under test and one or more adjacent devices surrounding the device under test. The self-heating effect model includes a reference thermal resistance and a reference thermal capacity; a thermal temperature feedback model used to acquire a thermal level of the device under test; a thermal resistance modification model used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and the reference thermal resistance; and a thermal capacity modification model used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and the reference thermal capacity.

First claim

What is claimed is:

1. A self-heating effect apparatus comprising:
a memory, storing program instructions for a self-heating effect model, and
a processor, coupled to the memory and, when executing the program instructions, configured to process the self-heating effect model for characterizing a heat flow network of devices, the devices including a device under test and one or more adjacent devices surrounding the device under test, wherein the self-heating effect model includes:
a thermal temperature feedback model, used to acquire a thermal level of the device under test, by thermal levels of the one or more adjacent devices, distance levels between the device under test and the one or more adjacent devices, a vertical thermal diffusion level of the device under test, a power level of the device under test, and an ambient temperature level of the device under test and the one or more adjacent devices;
a thermal resistance modification model, used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and a reference thermal resistance; and
a thermal capacity modification model, used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and a reference thermal capacity.

2. The apparatus according to claim 1 , wherein:
the thermal temperature feedback model comprises: a temperature level model for acquiring a temperature level of a device; and a thermal level model for acquiring a thermal level of the device.

3. The apparatus according to claim 2 , wherein:
temperature levels of the devices include a temperature level of the device under test and temperature levels of the one or more adjacent devices; and
thermal levels of the devices include a thermal level of the device under test and thermal levels of the one or more adjacent devices.

4. The apparatus according to claim 3 , wherein:
the thermal level of the device under test is denoted as TML(S 0 ) and acquired by the thermal level model, according to the temperature level, denoted as WTL(S 0 ), of the device under test and the power level, denoted as EPD(S 0 ), of the device under test, TML(S 0 )=(WTL(S 0 )+EPD(S 0 ))*ETR, wherein ETR is a thermal coefficient; and
the temperature level, denoted as WTL(S 0 ), of the device under test is acquired by the temperature level model, according to the distance levels between the device under test and the one or more adjacent devices, the thermal levels of the one or more adjacent devices, the vertical thermal diffusion level, denoted as VHD(S 0 ), of the device under test, and the ambient temperature level, denoted as ETS, of the device under test and the one or more adjacent devices

WTL
⁡

(

S
0

)

=

∑

i
=
1

k

⁢

⁢

W

i
⁢

⁢
0

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TML
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(

S
i

)

+

VHD
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(

S
0

)

+
ETS

,

wherein:
W i0 represents a distance level between the device under test and an i-th adjacent device;
TML(S i ) represents the thermal level of the i-th adjacent device; and
k equals to a total quantity of the one or more adjacent devices.

5. The apparatus according to claim 4 , wherein:
the thermal level, denoted as TML(S i ), of the i-th adjacent device is acquired by the thermal level model, according to the temperature level, denoted as WTL(S i ), of the i-th adjacent device and the power level, denoted as EPD(S i ), of the i-th adjacent device, TML(S i )=(WTL(S i )+EPD(S i ))*ETR; and
the temperature level, denoted as WTL(S i ), of the i-th adjacent device is acquired by the temperature level model, according to the distance level, denoted as W i0 , between the i-th adjacent device and the device under test, distance levels between the i-th adjacent device and adjacent devices surrounding the i-th adjacent device, the thermal level, denoted as TML(S 0 ), of the device under test, thermal levels of the adjacent devices surrounding the i-th adjacent device, the vertical thermal diffusion level, denoted as VHD(S i ), of the i-th adjacent device, and the ambient temperature, denoted as ETS, of the device under test and the one or more adjacent devices,

WTL
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m
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k
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1

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m
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TML
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Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Lin Xi
• Shen yi hua
• Li Sen Sheng

Classifications

• G06F30/30 Primary

  Circuit design · CPC title

• G01R31/00

  Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere ({measuring superconductive properties G01R33/1238;} testing line transmission systems H04B3/46; testing or measuring semiconductors or solid state devices during manufacture {H10P74/00}) · CPC title

• G01R31/2874

  related to temperature · CPC title

• G01R31/2849

  Environmental or reliability testing, e.g. burn-in or validation tests (of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855) · CPC title

• G06F2119/08

  Thermal analysis or thermal optimisation · CPC title