Solar cell and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11133426-B2
Application number	US-201916457129-A
Country	US
Kind code	B2
Filing date	Jun 28, 2019
Priority date	Nov 28, 2014
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A method for manufacturing a solar cell can include forming a tunneling layer on first and second surfaces of a semiconductor substrate, the tunneling layer including a dielectric material; forming a polycrystalline silicon layer on the tunnel layer at the first surface and on the second surface of the semiconductor substrate; removing portions of the tunnel layer and the polycrystalline silicon layer formed at the first surface of the semiconductor substrate; forming a doping region at the first surface of the semiconductor substrate by diffusing a dopant; forming a passivation layer on the polycrystalline silicon layer at the second surface of the semiconductor substrate; and forming a second electrode connected to the polycrystalline silicon layer by penetrating through the passivation layer.

First claim

What is claimed is:

1. A method for manufacturing a solar cell, the method comprising:
forming a tunneling layer on first and second surfaces of a semiconductor substrate, the tunneling layer including a dielectric material;
forming a polycrystalline silicon layer on the tunnel layer at the first surface and on the second surface of the semiconductor substrate;
removing portions of the tunnel layer and the polycrystalline silicon layer formed at the first surface of the semiconductor substrate;
forming a doping region at the first surface of the semiconductor substrate by diffusing a dopant;
forming a passivation layer on the polycrystalline silicon layer at the second surface of the semiconductor substrate; and
forming an electrode connected to the polycrystalline silicon layer by penetrating through the passivation layer,
wherein, in the removing the portions of the tunnel layer and the polycrystalline silicon layer, an isolation portion is formed at the second surface of the semiconductor substrate.

2. The method according to claim 1 , wherein the passivation layer is formed on the isolation portion.

3. The method according to claim 1 , wherein the passivation layer is directly formed on the second surface of the semiconductor substrate at the isolation portion.

4. The method according to claim 1 , wherein, in the forming the polycrystalline silicon layer, the polycrystalline silicon layer is formed by a low-pressure chemical vapor deposition method.

5. The method according to claim 4 , wherein, in the forming the polycrystalline silicon layer, the polycrystalline silicon layer is formed at a deposition temperature of 500° C. to 700° C.

6. The method according to claim 1 , further comprising:
doping the polycrystalline silicon layer with a first conductive type dopant.

7. The method according to claim 6 , wherein the doping the polycrystalline silicon layer is performed by a thermal treatment in a gas atmosphere including the first conductive type dopant.

8. The method according to claim 6 , wherein the polycrystalline silicon layer is intrinsic before the doping the polycrystalline silicon layer, and
wherein the doping the polycrystalline silicon layer includes a process forming a doping layer including the first conductive type dopant on the polycrystalline silicon layer while the polycrystalline silicon layer is intrinsic.

9. The method according to claim 8 , wherein the doping the polycrystalline silicon layer further includes a process diffusing the first conductive type dopant into the polycrystalline silicon layer while the polycrystalline silicon layer is intrinsic.

10. The method according to claim 1 , wherein, in the removing the portions of the tunnel layer and the polycrystalline silicon layer, the portions of the tunnel layer and the polycrystalline silicon layer are removed by reactive ion etching (RIE).

11. The method according to claim 1 , wherein, in the removing the portions of the tunnel layer and the polycrystalline silicon layer, the portions of the tunnel layer and the polycrystalline silicon layer are removed by wet etching.

12. The method according to claim 11 , wherein, in the removing the portions of the tunnel layer and the polycrystalline silicon layer, the portions of the tunnel layer and the polycrystalline silicon layer are removed using a mask.

13. The method according to claim 12 , wherein, in the removing the portions of the tunnel layer and the polycrystalline silicon layer, the mask is partially disposed on the polycrystalline silicon layer at the second surface of the semiconductor substrate so that the mask is not formed at an edge portion on the polycrystalline silicon layer at the second surface of the semiconductor substrate to form isolation portion at the edge portion of the second surface.

14. The method according to claim 12 , further comprising:
removing the mask after the removing the portions of the tunnel layer and the polycrystalline silicon layer.

15. The method according to claim 1 , wherein the tunneling layer is formed by a low-pressure chemical vapor deposition (LPCVD).

16. The method according to claim 15 , wherein the tunneling layer and the polycrystalline silicon layer are formed by an in-situ process consecutively forming the tunnel layer and the intrinsic semiconductor layer in a same deposition apparatus.

17. The method according to claim 1 , further comprising:
doping the first surface of the semiconductor substrate with a second conductive type dopant.

18. The method according to claim 17 , wherein the second conductive type dopant is diffused into the semiconductor substrate by thermal diffusion.

19. The method according to claim 18 , further comprising:
forming a capping layer on the polycrystalline silicon layer before the doping the first surface of the semiconductor substrate with the second conductive type dopant.

Assignees

• Lg Electronics Inc

Inventors

• Ha Jungmin
• Kim Sungjin
• Cheong Juhwa
• Ahn Junyong
• Choi Hyungwook
• Chang Wonjae
• Kim Jaesung

Classifications

• H10F71/133

  Providing edge isolation · CPC title

• H10F10/14

  Photovoltaic cells having only PN homojunction potential barriers · CPC title

• H10F10/165

  the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells · CPC title

• H10F77/1645

  including microcrystalline silicon · CPC title

• H10F77/937

  Busbar structures for modules · CPC title