Super-junction IGBT device and method for manufacturing same

Patent metadata

Field	Value
Publication number	US-11133407-B2
Application number	US-201916599741-A
Country	US
Kind code	B2
Filing date	Oct 11, 2019
Priority date	Jan 22, 2019
Publication date	Sep 28, 2021
Grant date	Sep 28, 2021

Abstract

A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced.

First claim

What is claimed is:

1. A method for manufacturing a super-junction insulated gate bipolar transistor (IGBT) device, wherein the method comprises the following front process steps:
Step 1 , forming a super-junction structure in an N-type epitaxial layer, wherein the super-junction structure is formed by a plurality of N-type pillars and P-type pillars which are alternately arrayed in a horizontal direction, and each said N-type pillar and the adjacent P-type pillar form a corresponding super-junction cell;
Step 2 , forming trench gates of device cell structures of the super-junction IGBT device, wherein the device cell structures are formed at tops of the super-junction cells, and the multiple device cell structures are connected in parallel to form the super-junction IGBT device; and wherein each said trench gate is formed through the following sub-steps:
Step 21 , forming a gate trench, wherein the gate trench extends across an interface of the corresponding P-type pillar and adjacent N-type pillar in the horizontal direction, a first side face of the gate trench is located in the corresponding P-type pillar, and a second side face of the gate trench is located in the corresponding adjacent N-type pillar;
Step 22 , forming a gate dielectric layer on a bottom surface and side faces of the gate trench; and
Step 23 , filling the gate trench with polysilicon,

so that a polysilicon gate is formed;
Step 3 , forming a P-type doped body region, wherein the body region is located at a top of the corresponding N-type pillar, a depth of the gate trench is greater than that of the body region, and channels are formed on a surface of the body region and covered by side faces of the polysilicon gates;
wherein adrift region is formed by the N-type pillar at a bottom of the body region and by the N-type epitaxial layer at a bottom of the N-type pillar; and
wherein the top of each N-type pillar is provided with one body region and two gate trenches located on two sides of the body region, and each body region is isolated from the P-type pillars on two sides of the body region by the corresponding gate trenches;
Step 4 , forming a source region on a surface of the body region by an N+ region; and
the method further comprising the following back process step to be executed after the front process step of forming a P-type doped collector region at a bottom of the N-type epitaxial layer, wherein bottoms of the P-type pillars are spaced from a top surface of the collector region.

2. The method for manufacturing the super-junction IGBT device according to claim 1 , wherein the super-junction structure is formed in Step 1 through the following sub-steps:
providing a first N-type epitaxial sub-layer, and forming first P-type sub-pillars in selected areas of the first N-type epitaxial sub-layer by photo-etching definition and ion implantation;
forming a second N-type epitaxial sub-layer on a surface of the first N-type epitaxial sub-layer by epitaxial growth, forming second P-type sub-pillars in selected areas of the second N-type epitaxial sub-layer by photo-etching definition and ion implantation, and superimposing the second P-type sub-pillars and the first P-type sub-pillars; and
repeating epitaxial growth of the second N-type epitaxial sub-layer and photo-etching definition and ion implantation of the second P-type sub-pillars, so that more N-type epitaxial sub-layers are superimposed, and more corresponding P-type sub-pillars are superimposed, the N-type epitaxial layer is formed by the superimposed N-type epitaxial sub-layers, the corresponding P-type pillars are formed by the superimposed P-type sub-pillars in the N-type epitaxial sub-layers, and the N-type pillars are formed by the N-type epitaxial layer between the P-type pillars.

3. The method for manufacturing the super-junction IGBT device according to claim 1 , wherein the super-junction structure is formed in Step 1 through the following sub-steps:
forming a plurality of super-junction trenches in the N-type epitaxial layer by photo-etching definition and etching; and
filling the super-junction trenches with a P-type epitaxial layer, so that the P-type pillars are formed, and the N-type pillars are formed by the N-type epitaxial layer between the P-type pillars.

4. The method for manufacturing the super-junction IGBT device according to claim 1 , wherein the method further comprises the following back process step:
forming an N-type doped field stop layer in the N-type epitaxial layer located on a front of the collector region, wherein a doping concentration of the field stop layer is greater than that of the N-type epitaxial layer, and a top surface of the field stop layer is spaced from a bottom surface of the corresponding P-type pillar.

5. The method for manufacturing a super-junction IGBT device according to claim 1 , wherein the N-type epitaxial layer is formed on a surface of a semiconductor substrate, and the collector region is formed through the following sub-steps:
thinning a back of the semiconductor substrate; and
conducting ion implantation on the back of the thinned semiconductor substrate, so that the collector region is formed.

6. The method for manufacturing the super-junction IGBT device according to claim 1 , wherein the dielectric layer in Step 22 is a gate oxide and is formed by thermal oxidization.

7. The method for manufacturing the super-junction IGBT device according to claim 1 , further comprising the following front process steps:
Step 5 , forming an interlayer film to cover surfaces of the source region, the polysilicon gate and the body region;
Step 6 , forming contact holes penetrating through the interlayer film in a top of the source region and in a top of the polysilicon gate;
Step 7 , forming a front metal layer on a surface of the interlayer film and patterning the front metal layer to form an emitter and a gate, wherein the emitter makes contact with the source region at a bottom of the emitter via the corresponding contact hole, and the gate makes contact with the polysilicon gate at a bottom of the gate via the corresponding contact hole; and
wherein the method further comprises the following back process step of forming a back metal layer on a bottom surface of the collector region, and forming a collector by the back metal layer.

8. The method for manufacturing the super-junction IGBT device according to claim 7 , wherein in Step 6 , a bottom of the contact hole corresponding to the emitter penetrates through the source region; before an opening of the contact hole corresponding to the emitter is filled with metal, a body lead-out region is formed by a P+ region on the surface of the body region located at the bottom of the contact hole corresponding to the emitter; and the emitter is connected with the body region through the body lead-out region.

9. A super-junction insulated gated bipolar transistor (IGBT) device comprising:
a super-junction structure formed by a plurality of N-type pillars and P-type pillars which are alternately arrayed in a horizontal direction, and each N-type pillar and adjacent P-type pillar forming a corresponding super-junction cell, wherein the super-junction structure is formed in an N-type epitaxial layer, and a P-type doped collector region is formed at a bottom of the N-type epitaxial layer; and wherein bottoms of the P-type pillars are spaced from a top surface of the collector region; and
device cell structures formed at tops of the super-junction cells, and the multiple device cell structures are connected in parallel to form the super-junction IGBT device;
each of the device cell structure comprising:
a trench gate comprising a gate trench, a gate dielectric layer formed on a bot

Assignees

• Shanghai Huahong Grace Semiconductor Mfg Corp

Inventors

• Zhang Xukun
• Xing Junjun
• Pan Jia
• Li Hao
• Lu Yi

Classifications

• H10D62/054

  by high energy implantations in bulk semiconductor bodies, e.g. forming pillars · CPC title

• H10D62/111

  Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures · CPC title

• H10D64/513

  within recesses in the substrate, e.g. trench gates, groove gates or buried gates · CPC title

• H10D64/231

  Emitter or collector electrodes for bipolar transistors · CPC title

• H10D12/038

  having a recessed gate, e.g. trench-gate IGBTs · CPC title