Mixer circuitry

US11128258B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11128258-B2
Application numberUS-202017115349-A
CountryUS
Kind codeB2
Filing dateDec 8, 2020
Priority dateDec 20, 2019
Publication dateSep 21, 2021
Grant dateSep 21, 2021

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  5. First independent claim

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Abstract

Official abstract text for this publication.

Differential mixer circuitry comprising: first and second input-voltage nodes and first and second input-current nodes; a passive network of impedances connected between the first and second input-voltage nodes and the first and second input-current nodes, and configured to convert first and second input-voltage signals received at the first and second input-voltage nodes, respectively, into first and second input-current signals provided at the first and second input-current nodes, respectively, the first and second input-voltage signals defining a differential input-voltage signal having an input frequency, and the first and second input-current signals defining a differential input-current signal; and a mixing stage configured to mix the differential input-current signal with at least one mixing signal having a corresponding mixing frequency and output a differential output signal having an output frequency dependent on the input frequency and each mixing frequency.

First claim

Opening claim text (preview).

The invention claimed is: 1. Differential mixer circuitry comprising: first and second input-voltage nodes and first and second input-current nodes; a passive network of impedances connected between the first and second input-voltage nodes and the first and second input-current nodes, and configured to convert first and second input-voltage signals received at the first and second input-voltage nodes, respectively, into first and second input-current signals provided at the first and second input-current nodes, respectively, the first and second input-voltage signals defining a differential input-voltage signal having an input frequency, and the first and second input-current signals defining a differential input-current signal; and a mixing stage configured to mix the differential input-current signal with at least one mixing signal having a corresponding mixing frequency and output a differential output signal having an output frequency dependent on the input frequency and each mixing frequency, wherein the passive network of impedances comprises: a tail node for connection to a voltage source; a first tail-side impedance connected between the first input-voltage node and the tail node and a first mixer-side impedance connected between the first input-voltage node and the first input-current node; and a second tail-side impedance connected between the second input-voltage node and the tail node and a second mixer-side impedance connected between the second input-voltage node and the second input-current node. 2. The differential mixer circuitry as claimed in claim 1 , comprising first and second output-current nodes, wherein: the mixing stage is connected between the first and second input-current nodes and the first and second output-current nodes, and is configured to mix the first and second input-current signals with the at least one mixing signal to generate first and second output-current signals at the first and second output-current nodes, respectively, and defining the differential output signal. 3. The differential mixer circuitry as claimed in claim 2 , wherein: the passive network of impedances forms a voltage-to-current conversion stage of the differential mixer circuitry; and/or the differential mixer circuitry comprises a current-to-voltage conversion stage connected to the output-current nodes and configured to convert the first and second output-current signals provided at the first and second output-current nodes, respectively, into first and second output-voltage signals also provided at the first and second output-current nodes, respectively. 4. The differential mixer circuitry as claimed in claim 2 , wherein the mixing stage comprises at least a first mixer sub-stage, where X≥2, and the first mixer sub-stage comprises: first and second arrays of switches each comprising X switches, X upstream nodes and X downstream nodes, the switches of each array connected between the upstream nodes and the downstream nodes, respectively, of that array along respective current paths, wherein: the upstream nodes of the first array of the first mixer sub-stage are connected to the first input-current node and the upstream nodes of the second array of the first mixer sub-stage are connected to the second input-current node; the downstream nodes of the first and second arrays of the first mixer sub-stage are connected to the output-current nodes along current paths arranged so that said first and second output-current signals are provided at the first and second output-current nodes, respectively; and in a first operation mode of the differential mixer circuitry, the at least one mixing signal comprises at least a first sub-stage mixing signal being an X-phase mixing signal and the switches of each array are configured to be controlled by respective phases of the first sub-stage mixing signal, optionally wherein: the mixing stage comprises at least a second mixer sub-stage comprising a plurality of arrays of switches each comprising Y switches, Y upstream nodes and Y downstream nodes, where Y≥2, the switches of each array connected between the upstream nodes and the downstream nodes, respectively, of that array along respective current paths; the downstream nodes of the first and second arrays of the first mixer sub-stage are connected to the output-current nodes along current paths arranged to pass via the switches of the arrays of the second mixer sub-stage so that said first and second output-current signals are provided at the first and second output-current nodes, respectively; and in the first operation mode, the at least one mixing signal comprises at least a second sub-stage mixing signal being a Y-phase mixing signal, and the switches of each array of the second mixer sub-stage are configured to be controlled by respective phases of the second sub-stage mixing signal. 5. Integrated circuitry such as an IC chip and/or ADC circuitry comprising the circuitry as claimed in claim 1 . 6. Differential mixer circuitry comprising: first and second input-voltage nodes and first and second input-current nodes; a passive network of impedances connected between the first and second input-voltage nodes and the first and second input-current nodes, and configured to convert first and second input-voltage signals received at the first and second input-voltage nodes, respectively, into first and second input-current signals provided at the first and second input-current nodes, respectively, the first and second input-voltage signals defining a differential input-voltage signal having an input frequency, and the first and second input-current signals defining a differential input-current signal; and a mixing stage configured to mix the differential input-current signal with at least one mixing signal having a corresponding mixing frequency and output a differential output signal having an output frequency dependent on the input frequency and each mixing frequency, wherein the passive network of impedances comprises: a tail node for connection to a voltage source; a first tail-side impedance connected between the first input-current node and the tail node and a first input-side impedance connected between the first input-current node and the first input-voltage node; and a second tail-side impedance connected between the second input-current node and the tail node and a second input-side impedance connected between the second input-current node and the second input-voltage node. 7. The differential mixer circuitry as claimed in claim 6 , comprising first and second output-current nodes, wherein: the mixing stage is connected between the first and second input-current nodes and the first and second output-current nodes, and is configured to mix the first and second input-current signals with the at least one mixing signal to generate first and second output-current signals at the first and second output-current nodes, respectively, and defining the differential output signal. 8. The differential mixer circuitry as claimed in claim 7 , wherein: the passive network of impedances forms a voltage-to-current conversion stage of the differential mixer circuitry; and/or the differential mixer circuitry comprises a current-to-voltage conversion stage connected to the output-current nodes and configured to convert the first and second output-current signals provided at the first and second output-current nodes, respectively, into first and second output-voltage signals also provided at the first and second output-current nodes, respectively. 9. The differential mixer circuitry as claimed in claim 7 , wherein the mixing stage comprises at least a first mixer sub-stage, where X≥2, and the first mixer sub-stage comprises: f

Assignees

Inventors

Classifications

  • Arrangements to linearise a transconductance stage of a mixer arrangement · CPC title

  • H03D7/166Primary

    using two or more quadrature frequency translation stages · CPC title

  • H03D7/1458Primary

    Double balanced arrangements, i.e. where both input signals are differential · CPC title

  • Gilbert multipliers · CPC title

  • Analog to digital conversion · CPC title

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What does patent US11128258B2 cover?
Differential mixer circuitry comprising: first and second input-voltage nodes and first and second input-current nodes; a passive network of impedances connected between the first and second input-voltage nodes and the first and second input-current nodes, and configured to convert first and second input-voltage signals received at the first and second input-voltage nodes, respectively, into fi…
Who is the assignee on this patent?
Socionext Inc
What technology area does this patent fall under?
Primary CPC classification H03D7/166. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 21 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).