Protection circuit for decoupling a low voltage circuitry from a high voltage circuitry

Patent metadata

Field	Value
Publication number	US-11128121-B2
Application number	US-201715856778-A
Country	US
Kind code	B2
Filing date	Dec 28, 2017
Priority date	Dec 28, 2017
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

An apparatus is provided which comprises: a protection circuitry coupled between: a node and a first circuitry that is to selectively output a first voltage, the node coupled to a second circuitry that is to selectively output a second voltage, the protection circuitry comprising: a pair of complementary parallel transistors coupled between the node and the first circuitry, the pair comprising first and second transistors, wherein a gate of the first transistor is to receive a control signal at the first voltage, and a third transistor to selectively couple a gate of the second transistor to the node, a gate of the third transistor to receive the control signal at the first voltage.

First claim

I claim:

1. An apparatus comprising:
a node; and
a protection circuitry coupled between: the node and a first circuitry that is to selectively output from a selection a first voltage or a ground voltage during operation of the first circuitry, wherein the node is coupled to a second circuitry that is to selectively output from a selection a second voltage or a ground voltage during operation of the second circuitry, and wherein the protection circuitry comprises:
a pair of complementary parallel transistors coupled between the node and the first circuitry, the pair comprising first and second transistors, wherein a gate of the first transistor is to receive a control signal at the first voltage; and
a third transistor to selectively couple a gate of the second transistor to the node, a gate of the third transistor to receive the control signal at the first voltage.

2. The apparatus of claim 1 , wherein the protection circuitry comprises:
a fourth transistor and a fifth transistor in series, wherein the fourth and fifth transistors are to selectively couple the gate of the second transistor to a ground terminal.

3. The apparatus of claim 2 , wherein:
a gate of the fourth transistor is to receive the control signal at the first voltage.

4. The apparatus of claim 2 , wherein:
a gate of the fifth transistor is to receive a mode signal that is based on an operational mode of the apparatus.

5. The apparatus of claim 4 , further comprising:
a circuitry to: generate the mode signal at a logical high value when the first circuitry is to be active, and generate the mode signal at a logical low value when the second circuitry is to be active.

6. The apparatus of claim 5 , wherein the logical high value substantially corresponds to the first voltage and the logical low value substantially corresponds to zero volts.

7. The apparatus of claim 2 , wherein:
the fourth transistor is a first thick gate N type Metal-Oxide-Semiconductor Field Effect Transistor (TGNMOS); and
the fifth transistor is a second TGNMOS.

8. The apparatus of claim 1 , wherein:
the first transistor, the second transistor, and the third transistor are thick gate transistors relative to another thin gate transistor in the apparatus.

9. The apparatus of claim 1 , wherein:
the first transistor is a thick gate N type Metal-Oxide-Semiconductor Field Effect Transistor (TGNMOS);
the second transistor is a first thick gate P type Metal-Oxide-Semiconductor Field Effect Transistor (TGPMOS); and
the third transistor is a second TGPMOS.

10. The apparatus of claim 1 , wherein:
the first voltage is substantially lower than the second voltage.

11. A system comprising:
a memory to store instructions;
a processor circuitry coupled to the memory, the processor circuitry to execute the instructions;
a wireless interface to allow the processor circuitry to communicate with another system;
a first circuitry to selectively output a first voltage to a node;
a second circuitry to selectively output from a selection a second voltage or a ground voltage during operation of the second circuitry, the processor circuitry to control an operation of one or both the first circuitry or the second circuitry;
a first transistor and a second transistor coupled between the node and the second circuitry, wherein a gate of the first transistor is to receive a control signal at the first voltage or the ground voltage during operation of the first circuitry; and
an arrangement to provide, to a gate of the second transistor, one of: substantially the first voltage or substantially zero volts.

12. The system of claim 11 , wherein the arrangement comprises:
a third transistor coupled between the gate of the second transistor and the node, a gate of the third transistor to receive the control signal at the first voltage.

13. The system of claim 12 , wherein the arrangement comprises:
one or more pull-down transistors between the gate of the second transistor and a ground terminal.

14. The system of claim 13 , wherein:
a gate of a first pull-down transistor of the one or more pull-down transistors is to receive the control signal at the first voltage.

15. The system of claim 14 , wherein:
a gate of a second pull-down transistor of the one or more pull-down transistors to receive a mode signal that is based on an operational mode of the first and second circuitries, the first pull-down transistor and the second pull-down transistor coupled in series.

16. The system of claim 15 , further comprising:
a circuitry to: generate the mode signal at substantially the second voltage when the second circuitry is to be active, and generate the mode signal at substantially zero volts when the first circuitry is to be active.

17. An apparatus comprising:
a first circuitry that is to selectively output from a selection a first voltage or a ground voltage, during operation of the first circuitry, at a first output terminal;
a second circuitry that is to selectively output from a selection a second voltage at a second output or a ground voltage, during operation of the second circuitry, terminal;
a pair of parallel transistors coupled between the first output terminal and the second output terminal, the pair comprising first and second transistors, wherein a gate of the first transistor is to receive a control signal at the first voltage; and
a third transistor to selectively couple a gate of the second transistor to the second output terminal, a gate of the third transistor to receive the control signal at the first voltage.

18. The apparatus of claim 17 , further comprising:
a fourth transistor and a fifth transistor in series, wherein the fourth and fifth transistors are to selectively couple the gate of the second transistor to a ground terminal.

19. The apparatus of claim 18 , wherein:
a gate of the fourth transistor is to receive the control signal at the first voltage.

20. The apparatus of claim 18 , wherein:
a gate of the fifth transistor is to receive a mode signal that is based on an operational mode of the apparatus.

21. An apparatus comprising:
a pass-gate having a first transistor controllable by a first node at a first voltage or a ground voltage, and a second transistor coupled in parallel to the first transistor and controllable by a second node at a second voltage, the second voltage higher than the first voltage;
a third transistor controllable by the first node, wherein the third transistor is coupled to the second node;
a fourth transistor controllable by the first node, wherein the fourth transistor is coupled to the second node, and the first and second transistors of the pass-gate;
a first circuitry coupled to the pass-gate at a first end of the pass-gate;
a second circuitry coupled to the pass-gate at a second end of the pass-gate, wherein the first circuitry operates at the first voltage while the second circuitry operates at the second voltage.

22. The apparatus of claim 21 comprises a fifth transistor coupled in series with the third transistor and a ground rail, wherein the fifth transistor is controllable by a mode signal.

23. The apparatus of claim 21 , wherein while the second circuitry is active and the first circuitry is inactive, substantially the first voltage is provided at a gate of the first transistor, and substantially the second voltage is provided at a gate of the second transistor.

24. The apparatus of claim 21 , wherein while the

Assignees

• Intel Corp

Inventors

• Gan Kim Sim

Classifications

• H03K19/017509 Primary

  Interface arrangements · CPC title

• H02H3/003

  responsive to reversal of power transmission direction (reversal of direct current H02H3/18) · CPC title

• H02H3/20 Primary

  responsive to excess voltage · CPC title