Crack-resistant semiconductor devices

Patent metadata

Field	Value
Publication number	US-11127656-B2
Application number	US-201816483884-A
Country	US
Kind code	B2
Filing date	Feb 14, 2018
Priority date	Feb 15, 2017
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A semiconductor device comprises a semiconductor body and an electrically conductive via which extends through at least a part of the semiconductor body, where the via has a lateral size which is given in a first lateral direction that is perpendicular to a vertical direction given by the main axis of extension of the via and where the via has a top side and a bottom side that faces away from the top side. The semiconductor device further comprises an electrically conductive etch-stop layer arranged at the bottom side of the via in a plane which is parallel to the first lateral direction, and at least one electrically conductive contact layer at the bottom side of the via in a plane which is parallel to the first lateral direction. The lateral extent in the first lateral direction of the etch-stop layer is larger than the lateral size of the via and the lateral extent in the first lateral direction of the contact layer is smaller than the lateral size of the via. Furthermore, the etch-stop layer is arranged between the electrically conductive via and the contact layer in the vertical direction.

First claim

The invention claimed is:

1. A semiconductor device, comprising:
a semiconductor body,
an electrically conductive via that extends through at least a part of the semiconductor body, wherein the electrically conductive via has a lateral size in a first lateral direction within the semiconductor body, wherein the first lateral direction is perpendicular to a vertical direction given by a main axis of extension of the electrically conductive via and where the via has a top side and a bottom side that faces away from the top side,
an electrically conductive etch-stop layer arranged at the bottom side of the electrically conductive via in a plane that is parallel to the first lateral direction, and
at least one electrically conductive contact layer at the bottom side of the electrically conductive via in a plane that is parallel to the first lateral direction and wherein each of the at least one electrically conductive contact layer is centered with respect to the via,
wherein a lateral extent in the first lateral direction of the electrically conductive etch-stop layer is larger than the lateral size of the electrically conductive via at the bottom side of the electrically conductive via,
wherein a lateral extent in the first lateral direction of the at least one electrically conductive contact layer is smaller than the lateral size in the first lateral direction of the electrically conductive via at the bottom side of the electrically conductive via within the semiconductor body, and
wherein the electrically conductive etch-stop layer is arranged between the electrically conductive via and the at least one electrically conductive contact layer in the vertical direction.

2. The semiconductor device according to claim 1 , wherein the lateral extent in the first lateral direction of the at least one electrically conductive contact layer is between 10 μm and 39 μm.

3. The semiconductor device according to claim 1 , wherein the at least one electrically conductive contact layer has a thickness in the vertical direction that is larger than a thickness of the electrically conductive etch-stop layer.

4. The semiconductor device according to claim 1 , wherein the semiconductor device comprises an electrically conductive top contact at a top contact side of the semiconductor device facing away from the top side of the electrically conductive via, wherein the electrically conductive top contact has a thickness in the vertical direction that is larger than a thickness of the electrically conductive etch-stop layer and a thickness of the at least one electrically conductive contact layer, respectively.

5. The semiconductor device according to claim 1 , wherein the electrically conductive etch-stop layer and of the at least one electrically conductive contact layer have the same thickness in the vertical direction.

6. The semiconductor device according to claim 1 , wherein the semiconductor device comprises at least two electrically conductive contact layers.

7. The semiconductor device according to claim 1 , wherein the electrically conductive etch-stop layer and the at least one electrically conductive contact layer are electrically connected by at least one electrically conductive connection.

8. The semiconductor device according to claim 1 , wherein at least one of the electrically conductive etch-stop layer or the at least one electrically conductive contact layer is electrically connected with an integrated circuit of the semiconductor device.

9. The semiconductor device according to claim 1 , wherein the at least one electrically conductive contact layer is a structured layer that is structured with an electrically non-conductive material that forms a grid.

10. The semiconductor device according to claim 1 , wherein at least one electrically conductive intermediate layer is arranged at the bottom side of the electrically conductive via in a plane that is parallel to the first lateral direction and wherein a lateral extent in the first lateral direction of the at least one electrically conductive intermediate layer is equal to or larger than the lateral size in the first lateral direction of the electrically conductive via within the semiconductor body.

11. The semiconductor device according to claim 10 , wherein the at least one electrically conductive intermediate layer is arranged between the electrically conductive etch-stop layer and the at least one electrically conductive contact layer in the vertical direction.

12. The semiconductor device according to claim 1 , wherein the electrically conductive via is formed by a trench that is at least partially coated with an electrically conductive contact material at inner walls of the trench.

13. The semiconductor device according to claim 12 , wherein an inner volume of the trench is free of the electrically conductive contact material.

14. The semiconductor device according to claim 13 , wherein the electrically conductive etch-stop layer is in electrical contact and mechanical contact with the electrically conductive contact material of the electrically conductive via.

15. The semiconductor device according to claim 1 , wherein a lateral extent in a second lateral direction of the at least one electrically conductive contact layer is larger than a lateral extent in the second lateral direction of the electrically conductive via.

16. The semiconductor device according to claim 1 , wherein the lateral extent in the first lateral direction of the at least one electrically conductive contact layer amounts to 25% to 99% of the lateral size in the first lateral direction of the electrically conductive via within the semiconductor body.

17. The semiconductor device according to claim 1 , wherein the lateral extent in the first lateral direction of the at least one electrically conductive contact layer amounts to 70% to 80% of the lateral size in the first lateral direction of the electrically conductive via within the semiconductor body.

18. The semiconductor device according to claim 1 , further comprising at least one wall of the electrically conductive via extending from the bottom side of the electrically conductive via wherein the at least one wall is substantially vertical.

19. The semiconductor device according to claim 1 , wherein:
the lateral extent in the first lateral direction of the electrically conductive etch-stop layer is larger than the lateral size of the electrically conductive via at any depth of the electrically conductive via, and
the lateral extent in the first lateral direction of the at least one electrically conductive contact layer is smaller than the lateral size in the first lateral direction of the electrically conductive via at any depth of the electrically conductive via within the semiconductor body.

Assignees

• Ams Ag

Inventors

• Kraft Jochen
• Parteder Georg
• Singulani Anderson
• Coppeta Raffaele
• Schrank Franz

Classifications

• H10W20/216

  characterised by dielectric material at least partially filling the via holes, e.g. covering the through-semiconductor vias in the via holes · CPC title

• H10W20/0234

  comprising etching via holes that stop on pads or on electrodes · CPC title

• H10W20/0242

  comprising etching via holes from the back sides of the chips, wafers or substrates · CPC title

• H10W72/944

  Dispositions of multiple bond pads · CPC title

• H10W72/942

  relative to underlying supporting features, e.g. bond pads, RDLs or vias · CPC title