Memory system with minimized heat generation which includes memory that operates at cryogenic temperature

Patent metadata

Field	Value
Publication number	US-11127451-B2
Application number	US-201916564837-A
Country	US
Kind code	B2
Filing date	Sep 9, 2019
Priority date	Nov 30, 2018
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

A memory system includes a voltage generator disposed in a high temperature region, and suitable for generating a first voltage; a memory disposed in a low temperature region, and suitable for using a second voltage; and a voltage converter disposed between the high temperature region and the low temperature region, suitable for converting the first voltage into the second voltage, and including a core made from a material having lower heat conductivity than a metal.

First claim

What is claimed is:

1. A memory system comprising:
a voltage generator disposed in a high temperature region, and configured to generate a first voltage;
a memory disposed in a low temperature region, and configured to use a second voltage; and
a voltage converter disposed between the high temperature region and the low temperature region, configured to convert the first voltage into the second voltage,
wherein, the voltage converter includes:
a core disposed between the high temperature region and the low temperature region,
a first coil coupled to the voltage generator and wound around a high temperature side of the core; and
a second coil coupled to the memory and wound around a lower temperature side of the core.

2. The memory system of claim 1 , wherein the low temperature region is a temperature of 77K or lower.

3. The memory system of claim 1 ,
further comprising an interface disposed between the high temperature region and the low temperature region, and configured to output voltage information corresponding to the second voltage to the voltage generator,
wherein the voltage generator generates the first voltage based on the voltage information.

4. The memory system of claim 3 , wherein the interface includes an opto-coupler.

5. The memory system of claim 3 , wherein the interface includes:
a transmitting circuit disposed in the low temperature region, and configured to generate transmission information based on the second voltage; and
a receiving circuit disposed in the high temperature region, and configured to generate the voltage information based on the transmission information.

6. The memory system of claim 3 , wherein the interface is activated in a first mode of the memory, and deactivated in a second mode of the memory.

7. The memory system of claim 6 ,
wherein the first mode includes one or more of a write mode, a read mode and a refresh mode,
wherein the second mode includes a power-down mode.

8. The memory system of claim 1 , further comprising:
a first cooler disposed in the high temperature region, and configured to generate a refrigerant; and
a second cooler disposed in the low temperature region, and configured to receive the refrigerant.

9. The memory system of claim 8 , wherein the refrigerant includes liquid nitrogen.

10. The memory system of claim 8 ,
wherein the first cooler includes a condenser,
wherein the second cooler includes an evaporator.

11. The memory system of claim 1 , wherein the core is made from a material having lower heat conductivity than a metal.

12. The memory system of claim 11 , wherein the material includes any one or a combination of plastic and ceramic.

13. The memory system of claim 1 , wherein the core includes a nonmetal.

14. A memory system comprising:
a voltage generator disposed in a high temperature region, and configured to generate a first voltage based on voltage information;
a memory disposed in a low temperature region, and configured to store a write data signal and outputting a read data signal by using a second voltage;
a first signal converter disposed in the low temperature region, and configured to generate a digital signal corresponding to the second voltage;
a voltage converter disposed between the high temperature region and the low temperature region, configured to convert the first voltage into the second voltage, and including a core made from a material having lower heat conductivity than a metal;
an interface disposed between the high temperature region and the low temperature region, and configured to generate a first information signal based on the read data signal and the digital signal, and generating the write data signal based on a second information signal;
a controller disposed in the high temperature region, and configured to output the first information signal as a feedback signal or processing the first information signal according to a read operation, and generating the second information signal according to a write operation; and
a second signal converter configured to generate the voltage information corresponding to the feedback signal.

15. The memory system of claim 14 , wherein the low temperature region is of a temperature of 77K or lower.

16. The memory system of claim 14 , wherein the material includes any one or a combination of plastic and ceramic.

17. The memory system of claim 14 , wherein the voltage converter further includes:
a first coil coupled to the voltage generator and wound around a high temperature side of the core; and
a second coil coupled to the memory and wound around a lower temperature side of the core.

18. The memory system of claim 14 , wherein the interface includes:
a selecting circuit disposed in the low temperature region, and configured to select any one of the digital signal and the read data signal based on a read control signal;
a first transmitting circuit disposed in the low temperature region, and configured to generate a first transmitting signal based on an output signal of the selecting circuit;
a first receiving circuit disposed in the high temperature region, and configured to generate the first information signal based on the first transmitting signal;
a second transmitting circuit disposed in the high temperature region, and configured to generate a second transmitting signal based on the second information signal; and
a second receiving circuit configured to generate the write data signal based on the second transmitting signal.

19. The memory system of claim 14 , wherein the interface further includes:
a first fiber-optic cable configured to transfer the first transmitting signal; and
a second fiber-optic cable configured to transfer the second transmitting signal.

20. The memory system of claim 14 , wherein the interface is activated in a first mode of the memory, and deactivated in a second mode of the memory.

21. The memory system of claim 14 ,
wherein the first mode includes one or more of a write mode, a read mode and a refresh mode,
wherein the second mode includes a power-down mode.

22. The memory system of claim 14 , further comprising:
a first cooler disposed in the high temperature region, and configured to generate a refrigerant; and
a second cooler disposed in the low temperature region, and configured to receive the refrigerant.

23. The memory system of claim 22 , wherein the refrigerant includes liquid nitrogen.

24. The memory system of claim 22 ,
wherein the first cooler includes a condenser,
wherein the second cooler includes an evaporator.

25. A cryogenic memory system including:
a voltage generator configured to generate a first voltage;
a cryogenic memory operable based on a second voltage; and
a voltage provider including a core made from a nonmetal, and configured to provide the cryogenic memory with the second voltage based on the first voltage received from the voltage generator, and to block heat transfer from a first temperature to a second temperature which is lower than the first temperature.

26. The cryogenic memory system of claim 25 , further comprising:
a first cooler configured to generate a refrigerant including liquid nitrogen; and
a second cooler configured to receive the refrigerant including the liquid nitrogen.

27. The memory system of claim 25 , wherein the nonmetal includes any one or a combination of plastic and ceramic.

Assignees

• Sk Hynix Inc

Inventors

• Lee Se-Won

Classifications

• H10W40/305

  the fluid being a liquefied gas, e.g. liquid nitrogen · CPC title

• G11C11/4076

  Timing circuits (for regeneration management G11C11/406) · CPC title

• F25D3/10

  using liquefied gases, e.g. liquid air {(for cooling semiconductor devices H10W40/305)} · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C7/10

  Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers · CPC title