Pixel circuit, driving method thereof and display panel

Patent metadata

Field	Value
Publication number	US-11127347-B2
Application number	US-201916649283-A
Country	US
Kind code	B2
Filing date	Sep 24, 2019
Priority date	Jan 2, 2019
Publication date	Sep 21, 2021
Grant date	Sep 21, 2021

Abstract

Embodiments of the present disclosure provide a pixel circuit, a driving method thereof, and a display panel. The pixel circuit comprises: a light-emitting element; a driving sub-circuit configured to generate a current for driving the light-emitting element to emit light; and a first and a second light emission controlling sub-circuit, configured to supply the current for driving the light-emitting element to emit light to a first terminal of the light-emitting element under a control of a first controlling signal, respectively; a driving controlling sub-circuit configured to provide a data signal to the driving sub-circuit under a control of a second controlling signal; and the resetting sub-circuit configured to reset the driving sub-circuit, the first terminal of the light-emitting element, and a second node with a first voltage, under a control of a first resetting signal and a second resetting signal.

First claim

We claim:

1. A pixel circuit, comprising:
a light-emitting element;
a driving sub-circuit configured to generate a current for driving the light-emitting element to emit light;
a first light emission controlling sub-circuit and a second light emission controlling sub-circuit, wherein the first light emission controlling sub-circuit is electrically coupled to the driving sub-circuit at a first node, and the second light emission controlling sub-circuit is electrically connected between the driving sub-circuit and a first terminal of the light-emitting element, and is electrically coupled to the driving sub-circuit at a second node, and wherein the first light emission controlling sub-circuit and the second light emission controlling sub-circuit are configured to receive a first controlling signal, and supply the current for driving the light-emitting element to emit light to the first terminal of the light-emitting element under a control of the first controlling signal;
a driving controlling sub-circuit electrically coupled to the driving sub-circuit, and configured to receive a data signal and a second controlling signal, and supply the data signal to the driving sub-circuit under a control of the second controlling signal; and
a resetting sub-circuit electrically coupled to the driving sub-circuit, and configured to receive a first voltage signal, a first resetting signal, and a second resetting signal, and reset the driving sub-circuit, the first terminal of the light-emitting element, and the second node with the first voltage signal under a control of the first resetting signal and the second resetting signal.

2. The pixel circuit of claim 1 , wherein the driving sub-circuit comprises a driving transistor, a first transistor, and a storage capacitor, wherein:
a gate of the driving transistor is electrically coupled to a third node, a first electrode of the driving transistor is electrically coupled to the first node, and a second electrode of the driving transistor is electrically coupled to the second node;
a gate of the first transistor is electrically coupled to receive a third controlling signal, a first electrode of the first transistor is electrically coupled to the third node, and a second electrode of the first transistor is electrically coupled to the second node; and
a first electrode of the storage capacitor is electrically coupled to receive a second voltage signal, and a second electrode of the storage capacitor is electrically coupled to the third node.

3. The pixel circuit of claim 2 , wherein the resetting sub-circuit comprises a second transistor, a third transistor, and a fourth transistor, wherein:
a gate of the second transistor is electrically coupled to receive the first resetting signal, a first electrode of the second transistor is electrically coupled to receive the first voltage signal, and a second electrode of the second transistor is electrically coupled to the third node,
a gate of the third transistor is electrically coupled to receive the second resetting signal, a first electrode of the third transistor is electrically coupled to receive the first voltage signal, and a second electrode of the third transistor is electrically coupled to a first terminal of the light-emitting element, and
a gate of the fourth transistor is electrically coupled to receive the first resetting signal, a first electrode of the fourth transistor is electrically coupled to receive the first voltage signal, and a second electrode of the fourth transistor is electrically coupled to the second node.

4. The pixel circuit of claim 3 , wherein the first light emission controlling sub-circuit comprises a fifth transistor, and the second light emission controlling sub-circuit comprises a sixth transistor, wherein:
a gate of the fifth transistor is electrically coupled to receive the first controlling signal, a first electrode of the fifth transistor is electrically coupled to receive the second voltage signal, and a second electrode of the fifth transistor is electrically coupled to the first node; and
a gate of the sixth transistor is electrically coupled to receive the first controlling signal, a first electrode of the sixth transistor is electrically coupled to the second node, and a second electrode of the sixth transistor is electrically coupled to the first terminal of the light-emitting element.

5. A display panel including a plurality of pixel units, at least one of the plurality of pixel units comprising the pixel circuit of claim 4 , wherein each of the at least one pixel unit comprises:
a substrate;
the first transistor, the third transistor, the fourth transistor, and the sixth transistor, each of which comprises:
an active layer comprising a first electrode area and a second electrode area, and a channel area between the first electrode area and the second electrode area;
a first insulating layer covering the active layer;
a gate layer disposed on the first insulating layer to be electrically insulated from the active layer; and
a second insulating layer covering the gate layer and the first insulating layer;
a shield connection layer comprising a first shield line and a second shield line, the first shield line electrically connecting the second electrode area of the third transistor with the second electrode area of the sixth transistor, and the second shield line electrically connecting the second electrode area of the fourth transistor with the first electrode area of the sixth transistor,
wherein at least one of the first and second shield lines has an orthographic projection on the substrate at least partially overlapping with an orthographic projection of the channel area of the first transistor on the substrate.

6. The display panel of claim 5 , wherein:
the third transistor is formed with a first through hole penetrating the first insulating layer and the second insulating layer of the third transistor, so as to expose a part of the second electrode area of the third transistor;
the sixth transistor is formed with a second through hole and a third through hole penetrating the first insulating layer and the second insulating layer of the sixth transistor, so as to expose a part of the first electrode area of the sixth transistor and a part of the second electrode area of the sixth transistor, respectively; and
the fourth transistor is formed with a fourth through hole penetrating the first insulating layer and the second insulating layer of the fourth transistor, so as to expose a part of the second electrode area of the fourth transistor,
wherein the first shield line electrically connects the second electrode area of the third transistor with the second electrode area of the sixth transistor through the first through hole and the third through hole, and the second shield line electrically connects the second electrode area of the fourth transistor with the first electrode area of the sixth transistor through the second through hole and the fourth through hole.

7. The pixel circuit of claim 2 , wherein the resetting sub-circuit comprises a second transistor and a third transistor, wherein:
a gate of the second transistor is electrically coupled to receive the first resetting signal, a first electrode of the second transistor is electrically coupled to receive the first voltage signal, and a second electrode of the second transistor is electrically coupled to the second node,
a gate of the third transistor is electrically coupled to receive the second resetting signal, a first electrode of the third transistor is electrically coupled to receive the first voltage signal, and a second electrode of the third transistor is electrically coupled to the first terminal of the light-emitting element.

8. The pixel c

Assignees

• Boe Technology Group Co Ltd
• Mianyang Boe Optoelectronics Tech Co Ltd

Inventors

• Huang Yinglong
• YANG Bingwei
• Gao Wenbao

Classifications

• G09G3/3225 Primary

  using an active matrix · CPC title

• G09G2320/0257

  Reduction of after-image effects · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title

• G09G2300/0814

  used for selection purposes, e.g. logical AND for partial update · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title