Solid-state image pickup element with dam to control resin outflow

Patent metadata

Field	Value
Publication number	US-11121112-B2
Application number	US-201816482435-A
Country	US
Kind code	B2
Filing date	Feb 19, 2018
Priority date	Mar 3, 2017
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

The present technology relates to a solid-state image pickup element, electronic equipment, and a semiconductor apparatus that make it possible to reduce a surface reflection in an area in which a slit is formed and improve flare characteristics. A solid-state image pickup element includes a pixel area in which a plurality of pixels is two-dimensionally arranged in a matrix, a chip mounting area in which a chip is flip-chip mounted, and a dam area that is arranged around the chip mounting area and in which one or more slits that block an outflow of a resin are formed. In the dam area, the same OCL as that in the pixel area is formed. The present technology can be applied to a solid-state image pickup element etc. in which a chip is flip-chip mounted, for example.

First claim

The invention claimed is:

1. A solid-state image pickup element, comprising:
a pixel area that comprises a plurality of pixels arranged two-dimensionally in a matrix;
a chip mounting area that comprises a chip which is flip-chip mounted; and
a dam area that, is around the chip mounting area, comprises at least one slit to block an outflow of a resin, wherein
the dam area comprises a first on-chip lens (OCL), and
the at least one slit is in the first OCL which is in the dam area.

2. The solid-state image pickup element according to claim 1 , further comprising a low reflection projection on a bottom surface of the at least one slit.

3. The solid-state image pickup element according to claim 2 , wherein the low reflection projection has a shape of a second OCL that is in the pixel area.

4. The solid-state image pickup element according to claim 2 , wherein the low reflection projection has a shape of a third OCL smaller than a second OCL in the pixel area.

5. The solid-state image pickup element according to claim 2 , wherein the low reflection projection has a shape of a third OCL different from a second OCL in the pixel area.

6. The solid-state image pickup element according to claim 1 , wherein
a size of the first OCL includes a size of an integral multiple of a size of a second OCL in the pixel area, and
the size of the first OCL is viewed in a plan view with a direction of viewing normal to an active surface of the chip.

7. The solid-state image pickup element according to claim 1 , wherein
the at least one slit blocks an outflow of the resin that covers an upper surface and side surfaces of the chip, and
the resin is a light-shielding resin.

8. The solid-state image pickup element according to claim 1 , wherein
the at least one slit blocks an outflow of the resin filled in a region in which the chip is flip-chip mounted, and
the resin is an underfill resin.

9. The solid-state image pickup element according to claim 1 , wherein an antireflection film is over an upper surface of the first OCL in the dam area.

10. An electronic, comprising:
a solid-state image pickup element that comprises:
a pixel area that comprises a plurality of pixels arranged two-dimensionally in a matrix,
a chip mounting area that comprises a chip which is flip-chip mounted, and
a dam area that, is around the chip mounting area, comprises at least one slit to block an outflow of a resin, wherein
the dam area comprises an on-chip lens (OCL), and
the at least one slit is in the OCL which is in the dam area.

11. A semiconductor apparatus, comprising:
an on-chip lens (OCL) area that comprises a first OCL in a matrix;
a chip mounting area that comprises a chip which is flip-chip mounted; and
a dam area that, is around the chip mounting area, comprising at least one slit to block an outflow of a resin, wherein
the dam area comprises a second OCL, and
the at least one slit is in the second OCL which is in the dam area.

Assignees

• Sony Semiconductor Solutions Corp

Inventors

• Fujimagari Junichiro
• Ohkubo Tomohiro

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W72/387

  Flow barriers · CPC title

• H10W72/073

  of die-attach connectors · CPC title