PCIe device peer-to-peer communications

Patent metadata

Field	Value
Publication number	US-11119957-B2
Application number	US-202016810944-A
Country	US
Kind code	B2
Filing date	Mar 6, 2020
Priority date	Feb 5, 2019
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device. The communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers.

First claim

What is claimed is:

1. A system comprising:
a first processor configured to initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a second processor that initiates the transfers;
wherein at least one transfer is initiated by a request originated by an application executed by the second processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

2. The system of claim 1 , wherein the communication arrangement is established in a PCIe fabric comprising one or more PCIe switch circuits.

3. The system of claim 1 , wherein the first PCIe device comprises a Graphics Processing Unit (GPU) and the second PCIe device comprises a storage device.

4. The system of claim 1 , wherein the communication arrangement is further established to detect additional transfers from the second PCIe device to one or more addresses corresponding to an address range for the first PCIe device, and redirect the additional transfers to the first PCIe device without passing the additional transfers through the second processor that initiates the additional transfers.

5. The system of claim 1 , wherein the address range of the second PCIe device is in addition to a memory mapped address range assigned to the second PCIe device within a memory space of the second processor during enumeration of the second PCIe device by the second processor.

6. The system of claim 1 , wherein a management driver executed by the second processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

7. The system of claim 1 , wherein the communication arrangement redirects the transfers from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

8. A method comprising:
initiating a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a host processor that initiates the transfers;
wherein at least one transfer is initiated by a request originated by an application executed by the host processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

9. The method of claim 8 , wherein the communication arrangement is established in a PCIe fabric comprising one or more PCIe switch circuits.

10. The method of claim 8 , wherein the first PCIe device comprises a Graphics Processing Unit (GPU) and the second PCIe device comprises a storage device.

11. The method of claim 8 , wherein a management driver of the host processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

12. The method of claim 8 , wherein the communication arrangement redirects the transfers from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

13. An apparatus comprising:
one or more computer readable storage media;
a processor operatively coupled with the one or more computer readable storage media; and
program instructions stored on the one or more computer readable storage media, that when executed by the processor, direct the processor to at least:
initiate a communication arrangement between a first peripheral component interconnect express (PCIe) device and a second PCIe device;
wherein the communication arrangement is configured to detect transfers from the first PCIe device to one or more addresses corresponding to an address range of the second PCIe device, and redirect the transfers to the second PCIe device without passing the transfers through a host processor that initiates the transfers;
wherein at least one transfer is initiated by a request originated by an application executed by the host processor to transfer data from the first PCIe device to the second PCIe device via a command that employs the communication arrangement.

14. The apparatus of claim 13 , wherein the communication arrangement is established over a PCIe fabric comprising one or more PCIe switch circuits.

15. The apparatus of claim 13 , wherein the address range of the second PCIe device is in addition to a memory mapped address range assigned to the second PCIe device within a memory space of the host processor during enumeration of the second PCIe device by the host processor.

16. The apparatus of claim 13 , wherein a management driver executed by the host processor interfaces with a first device driver associated with the first PCIe device at least to initiate a direct memory access (DMA) transfer via the first device driver with a destination address corresponding to the address range for the second PCIe device.

17. The apparatus of claim 13 , wherein the communication arrangement redirects the transfers from the first PCIe device directed to the one or more addresses corresponding to the address range for the second PCIe device at least in part by translating the one or more addresses into PCIe device physical addresses of the second PCIe device.

Assignees

• Liqid Inc

Inventors

• Cannata James Scott
• Long Christopher R
• Puri Sumit
• Schramm Bryan

Classifications

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F13/4234

  being a memory bus · CPC title

• G06F2213/0026

  PCI express · CPC title

• G06F13/4221

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title