Compiling device and method

Patent metadata

Field	Value
Publication number	US-11119741-B2
Application number	US-201816955113-A
Country	US
Kind code	B2
Filing date	Dec 19, 2018
Priority date	Dec 20, 2017
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

Some embodiments are directed to a compiler device ( 100 ) configured to identify a sub-graph ( 210 ) in a data flow graph having one or more output nodes marked as encoded and one or more output nodes marked as non-encoded, and to replace the sub-graph by an encoded first sub-graph ( 210.1 ), and a non-encoded second sub-graph ( 210.2 ), wherein the first sub-graph has only encoded output nodes, and the second sub-graph has only non-encoded output nodes.

First claim

The invention claimed is:

1. A compiler device comprising:
an input interface circuit, wherein the input interface circuit is arranged to receive a computer program representation; and
a processor circuit,
wherein the processor circuit is arranged to obtain a data flow graph representation from the computer program representation,
wherein the data flow graph comprises nodes,
wherein at least a portion of the nodes in the data flow graph are marked as encoded or as non-encoded,
wherein an encoded node represents an operation on encoded data,
wherein a non-encoded node represents an operation on non-encoded data,

wherein the processor circuit is arranged to amend the data flow graph by identifying a sub-graph in the data flow graph, wherein the sub-graph has at least one output nodes marked as encoded and at least one output nodes marked as non-encoded,
wherein the processor circuit is arranged to replace the sub graph by an encoded first sub-graph and a non-encoded second sub-graph,
wherein the encoded first sub-graph has only encoded output nodes, and the non-encoded second sub-graph has only non-encoded output nodes,
wherein the encoded first sub-graph and the non-encoded second sub-graph are selected from the sub-graph as further sub-graphs,
wherein the processor circuit is arranged to insert at least one insert nodes into the data flow graph, wherein the insert nodes represent an encoding operation before the encoded first sub-graph such that the encoded first sub-graph operates only on encoded data, and/or the insert nodes represent a decoding operation before the non-encoded second sub-graph such that the non-encoded second sub-graph operates only on non-encoded data,
wherein the processor circuit is arranged to obtain a compilation of the computer program representation from at least the amended data flow graph.

2. The compiler device as in claim 1 , wherein at least an input node of the sub-graph is duplicated in the encoded first sub-graph and the non-encoded second sub-graph.

3. The compiler device as in claim 1 , wherein the encoded first sub-graph and the non-encoded second sub-graph are a duplication of the sub-graph.

4. The compiler device as in claim 3 , wherein the compiler device performs a dead-code removal optimization on the amended sub-graph.

5. The compiler device as in claim 1 ,
wherein the encoded first sub-graph comprises first nodes,
wherein the first nodes are marked encoded,
wherein the non-encoded second sub-graph comprises second nodes,
wherein the second nodes are marked non-encoded.

6. The compiler device as in claim 1 , wherein the data flow graph is a static single assignment graph.

7. The compiler device as in claim 1 wherein the sub-graph consists of phi and copy nodes.

8. The compiler device as in claim 1 wherein the encoding is a homomorphic encryption.

9. The compiler device as in claim 1 ,
wherein the computer program representation identifies at least one nodes in the data flow graph as marked encoded or as non-encoded.

10. The compiler device as in claim 1 ,
wherein the sub-graph indicates a datum,
wherein the datum has multiple sources and multiple targets.

11. The compiler device as in claim 1 , wherein the sub-graph in the data flow graph has at least one inputs nodes marked as encoded and at least one input nodes marked as non-encoded.

12. The compiler device as in claim 1 ,
wherein the processor circuit is arranged to identify a flow node in the amended or un-amended data flow graph,
wherein the processor circuit is arranged to identify an operating node before the flow node,
wherein the processor circuit is arranged to identify an operating node after the flow node,
wherein the flow node is a phi node or a copy node,
wherein the processor circuit is arranged to remove the operating node from after the flow node,
wherein the processor circuit is arranged to insert at least one operating nodes before the flow node,
wherein the processor circuit is arranged to merge an inserted operating node with an encoding or decoding operation.

13. A compiler device comprising:
an input interface circuit, wherein the input interface circuit is arranged to receive a computer program representation; and
a processor circuit,
wherein the processor circuit is arranged to obtain a data flow graph representation from the computer program representation,
wherein the data flow graph comprises nodes,
wherein at least a portion of the nodes in the data flow graph is marked as encoded or as non-encoded,
wherein the processor circuit is arranged to identify a flow node in the amended or un-amended data flow graph,

wherein the processor circuit is arranged to identify an operating node before the flow node,
wherein the processor circuit is arranged to identify an operating node after the flow node,
wherein the flow node is selected from the group consisting of a copy node or a phi node,
wherein the copy node distributes an incoming value to at least one further nodes,
wherein the processor circuit is arranged to amend the data flow graph by:
removing the operating node from after the flow node and inserting at least one operating nodes before the flow node; and
merging the operation represented by an inserted operating node with the encoding or decoding operation, and

wherein the processor circuit is arranged to obtain a compilation of the computer program representation from at least the amended data flow graph.

14. A compiler method comprising:
receiving a computer program representation;
obtaining a data flow graph representation from the computer program representation,
wherein the data flow graph comprises nodes,
wherein at least part of the nodes in the data flow graph are marked as encoded or as non-encoded;

amending the data flow graph by identifying a sub-graph in the data flow graph,
wherein the data flow graph has at least one output nodes marked as encoded and at least one or more output nodes marked as non-encoded,
wherein an encoded node represents an operation on encoded data,
wherein a non-encoded node represents an operation on non-encoded data;
replacing the sub-graph by an encoded first sub-graph, and a non-encoded second sub graph,
wherein the encoded first sub-graph has only encoded output nodes,
wherein the non-encoded second sub-graph has only non-encoded output nodes,
wherein the encoded first sub-graph and the non-encoded second subgraph are selected from the sub-graphs as further sub-graphs;
inserting at least one insert nodes
wherein the at least one insert nodes represent an encoding operation before the encoded first sub-graph such that the encoded first sub-graph operates only on encoded data, and/or inserting at least one nodes representing a decoding operation before the non-encoded second sub-graph such that the non-encoded second sub-graph operates only on non-encoded data; and
obtaining a compilation of the computer program representation from at least the amended data flow graph.

15. A compiler method comprising:
receiving a computer program representation;
obtaining a data flow graph representation from the computer program representation, wherein at least a portion of the nodes in the data flow graph are marked as encoded or as non-encoded;
amending the data flow graph by identifying in the amended or un-amended data flow graph a flow node, an operating node before the flow node, and an operating node after the flow node,
wherein the flow node is a copy node or phi node,
wherein the copy node distributes an incoming value to at least one further nodes;
removing

Assignees

• Koninklijke Philips Nv

Inventors

• Mallon William Charles
• Pestrin Alan
• Garcia Morchon Oscar

Classifications

• G06F8/451

  Code distribution (considering CPU load at run-time G06F9/505; load rebalancing G06F9/5083) · CPC title

• G06F8/433 Primary

  Dependency analysis; Data or control flow analysis · CPC title

• G06F21/14 Primary

  against software analysis or reverse engineering, e.g. by obfuscation · CPC title