Glitch mitigation in selectable output current mirrors with degeneration resistors

Patent metadata

Field	Value
Publication number	US-11119524-B1
Application number	US-202016815505-A
Country	US
Kind code	B1
Filing date	Mar 11, 2020
Priority date	Mar 11, 2020
Publication date	Sep 14, 2021
Grant date	Sep 14, 2021

Abstract

A selectable output current mirror may include a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror. The selectable output current mirror may also include switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch and glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

First claim

What is claimed is:

1. A selectable output current mirror comprising:
a reference leg configured to generate a reference current;
an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises:
an output leg transistor;
a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg; and
a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror;

switch control circuitry configured to selectively enable and disable the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch; and
glitch mitigation circuitry coupled to the second non-gate terminal of the output leg transistor and configured to maintain the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

2. The selectable output current mirror of claim 1 , wherein the glitch mitigation circuitry comprises:
a buffer configured to generate the substantially-constant voltage at a buffer output; and
a holding path switch coupled between the buffer output and the second non-gate terminal of the output leg transistor;
wherein the glitch mitigation circuitry is further configured to selectively enable and disable the holding path switch from passing the substantially-constant voltage from the buffer output to the second non-gate terminal of the output leg transistor.

3. The selectable output current mirror of claim 2 , wherein the buffer comprises a flipped follower, wherein the flipped follower comprises:
a current source configured to generate the reference current;
a first transistor coupled at a first non-gate terminal of the first transistor to the current source and coupled at a gate terminal of the first transistor to a gate terminal of the output leg transistor; and
a second transistor coupled at a first non-gate terminal of the second transistor to a second non-gate terminal of the first transistor, coupled at a second non-gate terminal of the second transistor to the voltage source to the selectable output current mirror, and coupled at its gate terminal to the first non-gate terminal of the first transistor;
such that the flipped follower generates the substantially-constant voltage at the first non-gate terminal of the second transistor.

4. The selectable output current mirror of claim 2 , wherein the flipped follower further comprises a compensation capacitor coupled between the gate terminal of the second transistor and the second non-gate terminal of the second transistor.

5. The selectable output current mirror of claim 2 , wherein the switch control circuitry is configured to:
enable the holding path switch before a transition between disabling of the degeneration path switch and enabling of the degeneration path switch; and
disable the holding path switch after the transition between disabling of the degeneration path switch and enabling of the degeneration path switch.

6. The selectable output current mirror of claim 1 , wherein the reference leg comprises:
a reference leg transistor coupled via its gate terminal to a gate terminal of the output leg transistor, having its gate terminal and a first non-gate terminal of the reference leg transistor coupled together, and having the current source coupled to the first non-gate terminal of the reference leg transistor; and
a series combination of a second degeneration resistor and a second degeneration path switch coupled between a second non-gate terminal of the transistor and the voltage source to the selectable output current mirror.

7. The selectable output current mirror of claim 1 , wherein the glitch mitigation circuitry causes the substantially-constant voltage to be approximately equal to a voltage present at the second terminal of the output leg transistor during times in which the degeneration path switch is enabled.

8. A method comprising, in a selectable output current mirror comprising a reference leg configured to generate a reference current, an output leg electrically coupled to the reference leg in a manner such that the output leg is configured to generate at an output of the output leg an output current proportional to the reference current, wherein the output leg comprises an output leg transistor, a drain path switch coupled between a first non-gate terminal of the output leg transistor and the output of the output leg, and a series combination of a degeneration resistor and a degeneration path switch coupled between a second non-gate terminal of the output leg transistor and a voltage source to the selectable output current mirror;
selectively enabling and disabling the output leg from generating the output current by selectively enabling and disabling the drain path switch and the degeneration path switch; and
maintaining the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch.

9. The method of claim 8 , wherein maintaining the second non-gate terminal of the output leg transistor at a substantially-constant voltage during transitions between disabling of the degeneration path switch and enabling of the degeneration path switch comprises:
generating the substantially-constant voltage at a buffer output; and
selectively enabling and disabling a holding path switch coupled between the buffer output and the second non-gate terminal of the output leg transistor from passing the substantially-constant voltage from the buffer output to the second non-gate terminal of the output leg transistor.

10. The method of claim 9 , wherein the buffer output is generated by a buffer comprising a flipped follower, wherein the flipped follower comprises:
a current source configured to generate the reference current;
a first transistor coupled at a first non-gate terminal of the first transistor to the current source and coupled at a gate terminal of the first transistor to a gate terminal of the output leg transistor; and
a second transistor coupled at a first non-gate terminal of the second transistor to a second non-gate terminal of the first transistor, coupled at a second non-gate terminal of the second transistor to the voltage source to the selectable output current mirror, and coupled at its gate terminal to the first non-gate terminal of the first transistor;
such that the flipped follower generates the substantially-constant voltage at the first non-gate terminal of the second transistor.

11. The method of claim 9 , wherein the flipped follower further comprises a compensation capacitor coupled between the gate terminal of the second transistor and the second non-gate terminal of the second transistor.

12. The method of claim 9 , further comprising:
enabling the holding path switch before a transition between disabling of the degeneration path switch and enabling of the degeneration path switch; and
disabling the holding path switch after the transition between disabling of the degeneration path switch and enabling of the degeneration path switch.

13. The method of claim 8 , wherein the reference leg comprises:
a reference leg transistor c

Assignees

• Cirrus Logic Int Semiconductor Ltd
• Cirrus Logic Inc

Inventors

• Dougherty Christopher M
• Bhattacharya Anindya
• Pandey Vaibhav
• Ou Ying

Classifications

• H04R3/00

  Circuits for transducers (arrangements for producing a reverberation or echo sound G10K15/08; amplifiers H03F) · CPC title

• G05F3/262 Primary

  using field-effect transistors only · CPC title