Signal isolator with three state data transmission

Patent metadata

Field	Value
Publication number	US-11115244-B2
Application number	US-202016809825-A
Country	US
Kind code	B2
Filing date	Mar 5, 2020
Priority date	Sep 17, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A signal isolator integrated circuit package includes a first circuit having a first input and a first output, a second circuit having a second input and a second output, an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier. The signal isolator includes a comparator configured to compare the first input of the first circuit to the second output of the second circuit. The second output can be configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.

First claim

What is claimed is:

1. A signal isolator integrated circuit package comprising:
a first circuit having a first input and a first output;
a second circuit having a second input and a second output, wherein the first circuit is disposed on a first die and the second circuit is disposed on a second die, different from the first die;
an isolation barrier layer between the first circuit and the second circuit, wherein the second output of the second circuit is coupled to the first input of the first circuit through the isolation barrier; and
a comparison circuit configured to compare the first input of the first circuit to the second output of the second circuit,
wherein the second output is configured to convey at least three states, including a first state indicative of a logical high of an input signal received at the first input, a second state indicative of a logical low of the input signal, and a third state indicative of a fault condition.

2. The signal isolator of claim 1 , wherein the comparison circuit includes a comparator.

3. The signal isolator of claim 1 , wherein the second output is configured to convey at least three symbols, including a first symbol indicative of a logical high of an input signal received at the first input, a second symbol indicative of a logical low of the input signal, and a third symbol indicative of a parameter of the input signal.

4. The signal isolator of claim 3 , wherein the parameter of the input signal is at least one of: a clock signal corresponding to the input signal, a fault signal indicative of no input signal, or an error signal indicating that the first input does not equal the second input.

5. The signal isolator of claim 1 , further comprising a receiver feedback element between the second output and wherein the comparison circuit is configured to identify a null condition to trigger the third state.

6. The signal isolator of claim 1 , wherein the logical high is provided as a first amplitude and the logical low is provided as a second amplitude, different than the first amplitude, and wherein the third state comprises a third amplitude, different than the first amplitude and the second amplitude.

7. The signal isolator of claim 6 , wherein the third amplitude comprises zero.

8. The signal isolator of claim 1 , wherein the logical high is provided as a first pulse width and the logical low is provided as a second pulse width, different than the first pulse width, and wherein the third state comprises no output (zero).

9. The signal isolator of claim 1 , wherein the logical high is provided as a first pulse height and the logical low is provided as a second pulse height, different than the first pulse height, and wherein the third state comprises no output (zero) indicative of a fault condition.

10. The signal isolator of claim 1 , wherein the first output is further configured to convey at least a fourth state indicative of a second condition, different than the fault condition, that is indicative of a specific condition of the signal or of the signal isolator.

11. The signal isolator of claim 10 , wherein the fourth state is conveyed as a fourth amplitude, different than the first amplitude, different than the second amplitude, and different than the third amplitude.

12. The signal isolator of claim 1 , further comprising a timer coupled to the comparison circuit to sample the output of the comparison circuit at a specific time.

13. The signal isolator of claim 1 , wherein the first circuit is disposed on a first die and the second circuit is disposed on a second die, different from the first die.

14. The signal isolator of claim 1 , wherein the first circuit includes a third input and a third output, and the second circuit includes a fourth input and a fourth output, and wherein the first circuit includes a second comparison circuit configured to compare the third input of the first circuit to the fourth output of the second circuit.

15. The signal isolator of claim 1 , wherein the second circuit includes a third input and a third output, and the first circuit includes a fourth input and a fourth output, wherein the second circuit includes a second comparison circuit configured to compare the third input of the second circuit to the fourth output of the first circuit.

16. The signal isolator of claim 1 , further comprising a status output to convey a fault in at least one of the first circuit or the second circuit.

17. The signal isolator of claim 1 , further including a tri-state buffer configured to receive the second output of the second circuit and generate an external output for the signal isolator integrated circuit package.

18. A method implementing a signal isolator having a first circuit separated from a second circuit by an isolation barrier layer, the method comprising:
receiving an input signal at an input of the first circuit of the signal isolator, the input having a logical high or a logical low value;
providing an output signal at an output of the second circuit as at least one of three states, wherein a first state is indicative of the logical high of the input signal, a second state is indicative of the logical low of the input signal, and a third state is indicative of a first condition, wherein the first circuit is disposed on a first die and the second circuit is disposed on a second die, different from the first die; and
comparing the output of the second die to the input of the first die to provide a compared output.

19. The method of claim 18 , wherein the first state is indicated by a first amplitude, the second state is indicated by a second amplitude, and the third state is indicated by a third amplitude.

20. The method of claim 19 , wherein the third amplitude comprises zero.

21. The method of claim 19 , wherein the output signal further comprises a fourth state indicated by a fourth amplitude, indicative of a specific condition, different than the first condition.

22. The method of claim 18 , further comprising sampling the compared output when timer times out.

23. The method of claim 18 , further comprising embedding clock data within the output, such that the third state provides the clock signal as the first condition of the signal isolator.

24. The method of claim 18 , wherein the first state is indicated by a first symbol, the second state is indicated by a second symbol that is different from the first symbol, and the third state is indicated by a third symbol that is different from the first and second symbols.

25. The method of claim 18 , further including employing a tri-state buffer to receive the second output of the second circuit and generate an external output for the signal isolator integrated circuit package.

26. A method implementing a signal isolator having a first circuit separated from a second circuit by an isolation barrier, the first circuit having a first input and a first output, the second circuit having a second input and a second output, the method comprising:
receiving an input signal at the first input of the first circuit;
sending an output signal at the second output of the second circuit back, across the isolation barrier, to a comparison circuit;
comparing the output signal to the input signal by the comparison circuit; and
providing an output as one of at least three states, wherein a first state is indicative of a logical high of the input signal, a second state is indicative of log

Assignees

• Allegro Microsystems Llc

Inventors

• Briano Robert A
• Shahnani Pedram Sotoodeh
• Voisine Cory

Classifications

• H03K19/0002 Primary

  Multistate logic (H03K19/02 takes precedence) · CPC title

• H04L25/0266 Primary

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title

• H04B17/17

  Detection of non-compliance or faulty performance, e.g. response deviations (H04B17/18 takes precedence) · CPC title