Error detection

Patent metadata

Field	Value
Publication number	US-11115061-B2
Application number	US-202017010351-A
Country	US
Kind code	B2
Filing date	Sep 2, 2020
Priority date	Sep 4, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

A datum is written to a memory, by splitting a binary word, representative of the datum and an error correcting or detecting code, into a first part and a second part. The first part is written at a logical address in a first memory circuit. The second part is written at the logical address in a second memory circuit. The error correcting or detecting code is dependent on both the datum and the logical address.

First claim

The invention claimed is:

1. A method, comprising writing a datum in memory by:
splitting a binary word, representative of said datum and an error correcting or detecting code, into at least a first part and a second part; and
writing said first part at a logical address in a first memory circuit; and
writing said second part at said logical address in a second memory circuit, wherein said second memory circuit is different from said first memory circuit and is configured to store as many binary words as said first memory circuit;
wherein said error correcting or detecting code is dependent on both said datum and said logical address.

2. The method according to claim 1 , wherein said first part and said second part each have a same size.

3. The method according to claim 1 , wherein the binary word is a concatenation of said datum and said correcting or error detecting code.

4. The method according to claim 1 , wherein said datum and said logical address are supplied by a single first processor.

5. The method according to claim 1 , wherein said datum and said logical address are supplied by at least one second processor and a third processor.

6. The method according to claim 5 , wherein said datum supplied by the second processor is compared to said datum supplied by the third processor, and said logical address supplied by the second processor is compared to said logical address supplied by the third processor.

7. The method according to claim 5 , wherein the second processor supplies said logical address to one of said at least two memory circuits, and the third processor supplies said logical address to another of said at least two memory circuits.

8. The method according to claim 5 , wherein the second processor supplies said logical address to said at least two memory circuits.

9. The method according to claim 1 , wherein said first memory circuit and said second memory circuit each have a same size.

10. The method according to claim 1 , wherein internal control signals of said at least two memory circuits are compared.

11. The method according to claim 1 , further comprising reading the datum from the memory by:
reading said first part at the logical address from the first memory circuit; and
reading said second part at said logical address from the second memory circuit.

12. The method according to claim 11 , wherein reading further comprises concatenating said first and second parts read from said first and second memory circuits, respectively, to form a read binary word.

13. The method according to claim 12 , obtaining the datum by removing the error correcting or detecting code from the read binary word.

14. The method according to claim 13 , further comprising detecting an error in the datum by computing the error correcting or detecting code again from the datum read from the memory.

15. The method according to claim 14 , further comprising verifying the error correcting or detecting code.

Assignees

• St Microelectronics Rousset
• St Microelectronics Alps Sas

Inventors

• Romain Fabrice
• Lisart Mathieu
• Arnould Patrick

Classifications

• H03M13/2906 Primary

  using block codes (H03M13/2957 takes precedence) · CPC title

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G06F11/0727 Primary

  in a storage system, e.g. in a DASD or network based storage system (drivers for digital recording or reproducing units G06F3/06; circuits for error detection or correction within digital recording or reproducing units G11B20/18; for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS], H04L67/1097) · CPC title

• G06F11/1076

  Parity data used in redundant arrays of independent storages, e.g. in RAID systems · CPC title