Voltage-to-time converter and method for reducing parasitic capacitance and power supply influences

US11115039B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11115039-B2
Application numberUS-201917057702-A
CountryUS
Kind codeB2
Filing dateMay 13, 2019
Priority dateMay 23, 2018
Publication dateSep 7, 2021
Grant dateSep 7, 2021

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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Abstract

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The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by using the compensation sampling network. A sampling common-mode level of the compensation sampling network is compensated, such that the influence of the low-frequency disturbance of a power supply voltage on a threshold of a traditional VTC threshold detection circuit is reduced. The output swing amplitude of the voltage-to-time converter of the present disclosure can reduce the influence of a parasitic capacitance. A voltage common-mode level of a VTC input end is related to a power supply voltage, which reduces a conversion error caused by the influence of the power supply voltage on a threshold.

First claim

Opening claim text (preview).

The invention claimed is: 1. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply, comprising: a main sampling network, to sample a main input signal and a main reference level; a compensation sampling network, to sample a compensation input signal and a compensation reference level; the main sampling network comprises a main sampling capacitor and a main sampling common-mode level, the main sampling common-mode level samples and converts a difference between an input voltage and a reference voltage; the compensation sampling network comprises a compensation sampling capacitor and a compensation sampling common-mode level, the compensation sampling common-mode level samples and converts the difference between the input voltage and a reference level, and compensates the input voltage; a discharge network, to discharge the main sampling capacitor and the compensation sampling capacitor; an over-threshold detection unit, to detect whether the output level of the discharge network exceeds the threshold and convert an input level into time. 2. The voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 1 , wherein in a sampling stage, the main sampling network and the compensation sampling network simultaneously sample the input voltage; in a conversion stage, the compensation sampling network is connected to the main sampling network, and performs voltage-time domain conversion simultaneously with the main sampling network. 3. The voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 2 , wherein in the conversion phase, a relationship between a voltage of an input end of the over-threshold detection unit and the input voltage is: V T ⁢ C ⁢ D = C C ⁢ M ⁢ S ⁢ P ⁡ ( C S + C P ) + V CC ⁢ C C C C + C S + C P + ( V REF - V I ⁢ N ) ⁢ C S + C C C C + C S + C P V TCD is the voltage of the input end of the over-threshold detection unit, V CMSP is a main sampling common-mode level, V IN is the input voltage, V REF is a reference voltage, V CC is a compensation sampling common-mode level, C S is a main sampling capacitance, C C is a compensation sampling capacitance, CP is a parasitic capacitance at the input end of the over-threshold detection unit. 4. A voltage-to-time converter for reducing influences of parasitic capacitance and power supply according to claim 3 , wherein a relationship between the compensation sampling common-mode level V CC and a power supply voltage V DD , and a relationship between a voltage threshold V TH of the over-threshold detection unit and the power supply voltage V DD are: { V CC = C C + C S + C P C C ⁢ V T ⁢ H = C C + C S + C P C C

Assignees

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Classifications

  • H03M1/54Primary

    Input signal sampled and held with linear return to datum · CPC title

  • in AC or DC supplies (G01R19/16519 and G01R19/16528 take precedence) · CPC title

  • Means for adapting the input signal to the range the converter can handle, e.g. limiting, pre-scaling (H03M1/18 takes precedence); Out-of-range indication · CPC title

  • H03M1/1245Primary

    Details of sampling arrangements or methods · CPC title

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What does patent US11115039B2 cover?
The present disclosure provides a voltage-to-time converter and method for reducing parasitic capacitance and power supply influences. The voltage-to-time converter includes: a main sampling network, a compensation sampling network, a discharge network and an over-threshold detection unit. The influence of a traditional VTC parasitic capacitance on a VTC output swing amplitude is reduced by usi…
Who is the assignee on this patent?
No 24 Research Institute Of China Electronics Tech Group Corporation
What technology area does this patent fall under?
Primary CPC classification H03M1/54. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Sep 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 2 related publications on this page (citations in our corpus or others sharing the same primary CPC).