Method for managing the startup of a phase-locked loop and corresponding integrated circuit

Patent metadata

Field	Value
Publication number	US-11115038-B2
Application number	US-202016923335-A
Country	US
Kind code	B2
Filing date	Jul 8, 2020
Priority date	Jul 9, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

First claim

The invention claimed is:

1. A method for operating a phase-locked loop (PLL) circuit, comprising:
delivering a reference signal for a phase comparator of the PLL circuit;
resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;
outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and
during startup, increasing a control voltage of the voltage-controlled oscillator in response to each control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;
after startup is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each control pulse.

2. The method according to claim 1 , wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two.

3. A method for operating a phase-locked loop (PLL) circuit, comprising:
delivering a reference signal for a phase comparator of the PLL circuit;
resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal;
outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and
increasing a control voltage of the voltage-controlled oscillator in response to each control pulse;
wherein increasing the control voltage of the voltage-controlled oscillator comprises applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator;
wherein the resistive capacitive filter comprises:
a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the voltage-controlled oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and
a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance;
the first capacitance being equal to a value that is A times the second capacitance, and the first resistance being equal to a value that is A times the second resistance; and

wherein said pre-charging current is applied to said intermediate node.

4. The method according to claim 1 , further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

5. The method according to claim 4 , further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.

6. The method according to claim 5 , further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

7. The method according to claim 4 , wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.

8. The method according to claim 7 , further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

9. A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to:
during the startup phase, increase a control voltage of the voltage-controlled oscillator during said control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator, but
after the startup phase is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each pulse.

10. A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;
wherein the delivery circuit comprises:
an input configured to receiving an initial reference signal;
a divide-by-two divider connected to said input; and
an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and
another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.

11. A phase-locked loop (PLL) circuit, comprising:
a phase comparator;
a voltage-controlled oscillator;
a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator;
a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator;
a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal;
wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and
a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse;
wherein the control circuit comprises:
a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-c

Assignees

• St Microelectronics Rousset

Inventors

• Gailhard Bruno
• Truphemus Laurent
• Eva Christophe

Classifications

• H03L7/199 Primary

  with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation · CPC title

• H03L7/1072

  by changing characteristics of the charge pump, e.g. changing the gain · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03L7/085 Primary

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title