Signal detection circuit and signal detection method

Patent metadata

Field	Value
Publication number	US-11115034-B2
Application number	US-202016993275-A
Country	US
Kind code	B2
Filing date	Aug 14, 2020
Priority date	Sep 26, 2019
Publication date	Sep 7, 2021
Grant date	Sep 7, 2021

Abstract

The present invention provides a signal detection circuit, wherein the signal detection circuit includes a sampling circuit and a determination circuit. In the operations of the signal detection circuit, the sampling circuit uses a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal. The determination circuit refers to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip includes the signal detection circuit.

First claim

What is claimed is:

1. A signal detection circuit, comprising:
a sampling circuit, configured to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal; and
a determination circuit, coupled to the sampling circuit, configured to refer to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip, wherein the chip comprises the signal detection circuit;
a clock signal generating circuit, configured to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

2. The signal detection circuit of claim 1 , wherein the plurality of clock signals comprise a first clock signal and a second clock signal, a phase difference between the first clock signal and the second clock signal is greater than a transition time of the input signal, and the phase difference between the first clock signal and the second clock signal is less than a difference between a period of the input signal and the transition time.

3. The signal detection circuit of claim 2 , wherein the plurality of clock signals further comprise a third clock signal, a difference between a first phase different and a second phase difference is greater than the transition time of the input signal, and the difference between the first phase different and the second phase difference is less than the difference between the period of the input signal and the transition time, wherein the first phase difference is the phase difference between the first clock signal and the second clock signal, and the second phase difference is a phase difference between the second clock signal and the third clock signal.

4. The signal detection circuit of claim 1 , wherein the sampling circuit comprises latches to use the plurality of clock signals to sample the input signal to generate the sampling result.

5. The signal detection circuit of claim 4 , wherein the sampling circuit comprises:
a first latching-type sampling circuit, configured to use the plurality of clock signals to sample the input signal to generate the sampling result.

6. The signal detection circuit of claim 5 , wherein the input signal is a differential signal comprising a first input signal and a second input signal, the first latching-type sampling circuit is configured to use the plurality of clock signals to sample the first input signal to generate a first sampled signal; and the sampling circuit further comprises:
a second latching-type sampling circuit, configured to use the plurality of clock signals to sample the second input signal to generate a second sampled result; and
an output circuit, coupled to the first latching-type sampling circuit and the second latching-type sampling circuit, configured to generate the sampling result according to the first sampled result and the second sampled result.

7. A signal detection method, comprising:
using a sampling circuit to use a plurality of clock signals to sample an input signal to generate a sampling result, wherein the plurality of clock signals have different phases, and frequencies of the plurality of clock signals are lower than a frequency of the input signal; and
referring to the sampling result to determine if the input signal comprises valid data, so as to determine if the input signal comes from outside a chip;
using a clock signal generating circuit to generate the plurality of clock signals having different phases according to a reference clock signal, wherein the clock signal generating circuit sequentially outputs the plurality of clock signals having different phases to the sampling circuit, for the sampling circuit to use only one of the plurality of clock signals to sample the input signal at a time.

8. The signal detection method of claim 7 , wherein the plurality of clock signals comprise a first clock signal and a second clock signal, a phase difference between the first clock signal and the second clock signal is greater than a transition time of the input signal, and the phase difference between the first clock signal and the second clock signal is less than a difference between a period of the input signal and the transition time.

9. The signal detection method of claim 8 , wherein the plurality of clock signals further comprise a third clock signal, a difference between a first phase different and a second phase difference is greater than the transition time of the input signal, and the difference between the first phase different and the second phase difference is less than the difference between the period of the input signal and the transition time, wherein the first phase difference is the phase difference between the first clock signal and the second clock signal, and the second phase difference is a phase difference between the second clock signal and the third clock signal.

10. The signal detection method of claim 7 , wherein the step of using the plurality of clock signals to sample the input signal to generate the sampling result is performed by a sampling circuit comprising latches.

11. The signal detection method of claim 10 , wherein the input signal is a differential signal comprising a first input signal and a second input signal, and the step of using the plurality of clock signals to sample the input signal to generate the sampling result comprises:
using the plurality of clock signals to sample the first input signal to generate a first sampled result;
using the plurality of clock signals to sample the second input signal to generate a second sampled result; and
generating the sampling result according to the first sampled result and the second sampled result.

12. The signal detection circuit of claim 1 , wherein the clock signal generating circuit comprises:
an oscillator, configured to generate the reference clock signal;
a plurality of delay circuits, configured to generate the plurality of clock signals having different phases; and
a multiplexer, coupled to the plurality of delay circuits, configured to receive the plurality of clock signals and sequentially output the plurality of clock signals to the sampling circuit.

13. The signal detection circuit of claim 12 , wherein the plurality of delay circuits are connected in series, and output signals of a portion of the delay circuits serve as the plurality of clock signals.

14. The signal detection method of claim 7 , wherein the clock signal generating circuit comprises:
an oscillator, configured to generate the reference clock signal;
a plurality of delay circuits, configured to generate the plurality of clock signals having different phases; and
a multiplexer, coupled to the plurality of delay circuits, configured to receive the plurality of clock signals and sequentially output the plurality of clock signals to the sampling circuit.

15. The signal detection method of claim 14 , wherein the plurality of delay circuits are connected in series, and output signals of a portion of the delay circuits serve as the plurality of clock signals.

Assignees

• Realtek Semiconductor Corp

Inventors

• Chen Bing-Hung

Classifications

• G11C7/1087

  Data input latches · CPC title

• G11C27/02

  Sample-and-hold arrangements (G11C27/04 takes precedence) · CPC title

• H03L7/0807

  concerning mainly a recovery circuit for the reference signal · CPC title

• H03K3/356 Primary

  Bistable circuits · CPC title

• H03L7/091 Primary

  the phase or frequency detector using a sampling device (H03L7/087 takes precedence) · CPC title