Digitally assisted feedback loop for duty-cycle correction in an injection-locked pll
US-2019115925-A1 · Apr 18, 2019 · US
Ring voltage controlled oscillator (VCO) startup helper circuit
US11115005B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11115005-B2 |
| Application number | US-202016835778-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 31, 2020 |
| Priority date | Aug 28, 2019 |
| Publication date | Sep 7, 2021 |
| Grant date | Sep 7, 2021 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in parallel with the third and fourth inverters, and a first biasing resistor connected to a first node and coupled to an input of the first inverter. The first biasing resistor includes a first switch configured to set the first biasing resistor to about zero voltage.
First claim
Opening claim text (preview).
What is claimed is: 1. A ring voltage controlled oscillator (VCO) circuit, comprising: a first stage including a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter of the first stage connected in parallel with the third and fourth inverters of the first stage and the second inverter of the first stage connected in parallel with the third and fourth inverters of the first stage; a second stage connected in series with the first stage, the second stage including a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter of the second stage connected in parallel with the third and fourth inverters of the second stage and the second inverter of the second stage connected in parallel with the third and fourth inverters of the second stage; a first biasing resistor directly connected to an input of the first inverter of the first stage and an output of the second inverter of the first stage, providing a resisting bias associated with a node of the second inverter of the first stage; a second biasing resistor directly connected to an input of the second inverter of the first stage and an output of the first inverter of the first stage, providing a resisting bias associated with a node the first inverter of the first stage; a third biasing resistor directly connected to an input of the first inverter of the second stage and an output of the second inverter of the second stage, providing a resisting bias associated with a node of the second inverter of the second stage; and a fourth biasing resistor directly connected to an input of the second inverter of the second stage and an output of the first inverter of the second stage, providing a resisting bias associated with a node the first inverter of the second stage, wherein the first and second inverter of the first stage are sized larger than the third and fourth inverter of the first stage, and wherein the first and second inverter of the second stage are sized larger than the third and fourth inverter of the second stage. 2. The ring VCO circuit of claim 1 , wherein the first biasing resistor comprises a metal-oxide semiconductor (MOS). 3. The ring VCO circuit of claim 2 , wherein the first biasing resistor comprises a p-type MOS (PMOS)/n-type (NMOS) pair. 4. The ring VCO circuit of claim 1 , wherein the second biasing resistor comprises a PMOS/NMOS pair.
Assignees
Inventors
Classifications
using a reference signal directly applied to the generator · CPC title
with differential cells · CPC title
- H03K3/0231Primary
Astable circuits {(H03K3/0315 takes precedence)} · CPC title
the oscillator comprising a ring oscillator · CPC title
- H03L7/0805Primary
the loop being adapted to provide an additional control signal for use outside the loop · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US11115005B2 cover?
- A ring voltage controlled oscillator (VCO) circuit is herein provided. According to one embodiment, a ring VCO circuit includes a plurality of stages connected in series, wherein each stage includes a first inverter, a second inverter, a third inverter and a fourth inverter, the first inverter connected in parallel with the third and fourth inverters and the second inverter connected in paralle…
- Who is the assignee on this patent?
- Samsung Electronics Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H03K3/0231. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Sep 07 2021 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 4 related publications on this page (citations in our corpus or others sharing the same primary CPC).